CY7C1470BV25_11 CYPRESS [Cypress Semiconductor], CY7C1470BV25_11 Datasheet - Page 17

• Manufacturer Part Number: CY7C1470BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Identification Codes
Boundary Scan Exit Order (2 M × 36)
Document Number: 001-15032 Rev. *I
EXTEST
IDCODE
SAMPLE Z
RESERVED
SAMPLE/PRELOAD
RESERVED
RESERVED
BYPASS
Bit #
Instruction
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
165-ball ID
M1
M2
C1
D1
D2
G1
G2
N1
R1
R2
E1
E2
F1
F2
K1
L1
K2
L2
J1
J2
Code
000
001
010
011
100
101
110
111
Forces all SRAM outputs to High Z state. This instruction is not 1149.1-compliant.
Loads the ID register with the vendor ID code and places the register between TDI and TDO. This
operation does not affect SRAM operations.
Forces all SRAM output drivers to a High Z state.
Do Not Use: This instruction is reserved for future use.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload function and
is therefore not 1149.1-compliant.
Do Not Use: This instruction is reserved for future use.
Places the bypass register between TDI and TDO. This operation does not affect SRAM operations.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Captures IO ring contents. Places the boundary scan register between TDI and TDO.
Do Not Use: This instruction is reserved for future use.
Bit #
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
165-ball ID
M10
P10
R10
R11
N11
M11
L10
K11
L11
R3
P2
R4
P6
R6
R8
P3
P4
P8
P9
R9
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Description
CY7C1472BV25, CY7C1474BV25
165-ball ID
D10
G10
K10
H11
G11
E11
D11
C11
F10
E10
A10
B10
J10
F11
J11
A9
B9
A8
B8
A7
CY7C1470BV25
Bit #
61
62
63
64
65
66
67
68
69
70
71
Page 17 of 29
165-ball ID
B7
B6
A6
B5
A5
A4
B4
B3
A3
A2
B2
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