CY7C1470BV25_11 CYPRESS [Cypress Semiconductor], CY7C1470BV25_11 Datasheet - Page 11

• Manufacturer Part Number: CY7C1470BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

Partial Write Cycle Description
The partial write cycle description for CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 follows.
Notes
Document Number: 001-15032 Rev. *I
Function (CY7C1470BV25)
Read
Write – No bytes written
Write Byte a – (DQ
Write Byte b – (DQ
Write Bytes b, a
Write Byte c – (DQ
Write Bytes c, a
Write Bytes c, b
Write Bytes c, b, a
Write Byte d – (DQ
Write Bytes d, a
Write Bytes d, b
Write Bytes d, b, a
Write Bytes d, c
Write Bytes d, c, a
Write Bytes d, c, b
Write All Bytes
Function (CY7C1472BV25)
Function (CY7C1474BV25)
Read
Write – No Bytes Written
Write Byte X(DQ
Write All Bytes
8. X = “Don't Care”, H = Logic HIGH, L = Logic LOW, CE stands for ALL Chip Enables active. BW
9. Write is defined by WE and BW
10. When a write cycle is detected, all IOs are tri-stated, even during Byte Writes.
11. Table lists only a partial listing of the Byte Write combinations. Any combination of BW
Read
Write – No Bytes Written
Write Byte a – (DQ
Write Byte b – (DQ
Write Both Bytes
signifies that the desired Byte Write Selects are asserted, see
c
a
b
d
x
a
b
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
and DQP
[a:d]
c
a
d
x)
b
)
. See
)
)
a
b
)
)
)
Partial Write Cycle Description
Partial Write Cycle Description
for details.
WE
WE
WE
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
[a:d]
is valid. Appropriate write is based on which Byte Write is active.
BW
for details.
CY7C1472BV25, CY7C1474BV25
x
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
L
= L signifies at least one Byte Write Select is active, BW
d
BW
H
H
L
L
x
b
BW
LL
H
H
H
H
H
H
H
H
X
L
L
L
L
L
L
L
c
All BW = L
BW
H
L
x
[8, 9, 10, 11]
x
CY7C1470BV25
BW
X
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
b
BW
H
H
x
L
L
Page 11 of 29
a
BW
x
X
H
H
H
H
H
H
H
H
= Valid
L
L
L
L
L
L
L
L
a
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