CY7C1470BV25_11 CYPRESS [Cypress Semiconductor], CY7C1470BV25_11 Datasheet - Page 15

• Manufacturer Part Number: CY7C1470BV25_11
• Description: 72-Mbit (2 M x 36/4 M x 18/1 M x 72) Pipelined SRAM with NoBL Architecture
• Manufacturer: CYPRESS [Cypress Semiconductor]

TAP AC Switching Characteristics
Over the Operating Range
Notes
Document Number: 001-15032 Rev. *I
Clock
t
t
t
t
Output Times
t
t
Setup Times
t
t
t
Hold Times
t
t
t
12. t
13. Test conditions are specified using the load in TAP AC Test Conditions. t
TCYC
TF
TH
TL
TDOV
TDOX
TMSS
TDIS
CS
TMSH
TDIH
CH
Parameter
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
TCK Clock Cycle Time
TCK Clock Frequency
TCK Clock HIGH time
TCK Clock LOW time
TCK Clock LOW to TDO Valid
TCK Clock LOW to TDO Invalid
TMS Setup to TCK Clock Rise
TDI Setup to TCK Clock Rise
Capture Setup to TCK Rise
TMS Hold after TCK Clock Rise
TDI Hold after Clock Rise
Capture Hold after Clock Rise
[12, 13]
Description
R
/t
F
= 1 ns.
CY7C1472BV25, CY7C1474BV25
Min
50
20
20
5
–
–
0
5
5
5
5
5
CY7C1470BV25
Max
20
10
–
–
–
–
–
–
–
–
–
–
Page 15 of 29
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback