M29DW641F70N1 NUMONYX [Numonyx B.V], M29DW641F70N1 Datasheet - Page 14

• Manufacturer Part Number: M29DW641F70N1
• Description: 64 Mbit (4Mb x16, Multiple Bank, Page, Boot Block) 3V Supply Flash Memory
• Manufacturer: NUMONYX [Numonyx B.V]

Signal descriptions
2.7
2.8
14/80
technique (In-System or Programmer technique). See
details.
The V
become unreliable. A 0.1µF capacitor should be connected between the V
pin and the V
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
I
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all the blocks previously protected using a High voltage
Block Protection technique (In-System or Programmer technique).
Note that if V
even if RP is at V
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, V
least t
If RP is asserted during a Program or Erase Operation, the RB pin remains Low (busy), until
the internal Reset Operation is completed, which requires a t
Reset/Block Temporary Unprotect during Program/Erase Operation AC waveforms
signal can be monitored by the system microprocessor to determine whether the Reset
Operation is completed or not.
If RP is asserted when no Program or Erase Operation is ongoing, the RB pin remains high,
V
to High, V
Holding RP at V
voltage Block Protection technique. Program and Erase Operations on all blocks will be
possible. The transition from V
See the Ready/Busy Output section,
characteristics
Operation AC waveforms
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase Operation. During Program or Erase Operations
Ready/Busy is Low, V
mode and Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write Operations cannot begin until
Ready/Busy becomes high-impedance. See
Temporary Unprotect during Program/Erase Operation AC waveforms
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
PP
IH
.
. A t
PP
PLPX
PHEL
/Write Protect pin must not be left floating or unconnected or the device may
IH
.
. After this delay, the memory is ready for Bus Read and Bus Write Operations.
or t
PP
SS
and
/WP is at V
PHGL
ID
Ground pin to decouple the current surges from the power supply. The PCB
ID
will temporarily unprotect all the blocks previously protected using a High
.
Figure 18: Reset/Block Temporary Unprotect during Program/Erase
delay elapses before the Reset Operation is completed and RP returns
OL
. Ready/Busy is high-impedance during Read mode, Auto Select
for more details.
IL
, then the four outermost parameter blocks will remain protected
IH
to V
ID
Table 24: Reset/Block Temporary Unprotect AC
must be slower than t
Table 24
and
Table 6: Hardware Protection
Figure 18: Reset/Block
PLYH
PHPHH
time (see
.
.
PP
Figure 18:
/Write Protect
M29DW641F
). The RB
IL
for
, for at