MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 51

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

NOTES (continued)
23. The refresh period 64ms. This equates to an
24. The I/O capacitance per DQS and DQ byte/
25. The valid data window is derived by achieving
26. Referenced to each output group: x4 = DQS with
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
average refresh rate of 15.625µs. However, an
AUTO REFRESH command must be asserted at
least once every 140.6µs; burst refreshing or
posting by the DRAM controller greater than
eight refresh cycles is not allowed.
group will not differ by more than this maxi-
mum amount for any given device.
other specifications -
t
derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is
uncertain when operating beyond a 45/55 ratio.
The data valid window derating curves are
provided below for duty cycles ranging between
50/50 and 45/55.
DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 =
LDQS with DQ0-DQ7; and UDQS with
DQ8-DQ15.
QH (
t
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
QH =
50/50
3.750
t
2.500
HP -
3.400
—— -75 @
—— -8 @
—— -75 @
—— -8 @
#
u
n
l
49.5/50.5
t
QHS). The data valid window
3.700
t
t
CK = 10ns
CK = 8ns
t
t
3.350
CK = 7.5ns
2.463
t
CK = 10ns
HP (
t
CK/2),
49/51
3.650
2.425
3.300
t
48.5/52.5
DQSQ, and
3.600
3.250
2.388
DERATING DATA VALID WINDOW
48/52
3.550
2.350
3.200
(
Clock Duty Cycle
t
QH -
51
47.5/53.5
t
DQSQ)
3.500
2.313
3.150
27. This limit is actually a nominal value and does
28. To maintain a valid level, the transitioning edge
29. The Input capacitance per pin group will not
30. JEDEC specifies CK and CK# input slew rate must
31. DQ and DM input slew rates must not deviate
not result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
of the input must:
a) Sustain a constant slew rate from the current
b) Reach at least the target AC level.
c) After the AC target level is reached, continue
differ by more than this maximum amount for
any given device..
be ≥ 1V/ns (2V/ns differentially).
from DQS by more than 10%. If the DQ/DM/
DQS slew rate is less than 0.5V/ns, timing must
be derated: 50ps must be added to
for each 100mv/ns reduction in slew rate. If slew
rate exceeds 4V/ns, functionality is uncertain.
47/53
3.450
AC level through to the target AC level, V
or V
to maintain at least the target DC level, V
or V
2.275
3.100
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IH
(
(
46.5/54.5
AC
DC
3.400
).
).
2.238
3.050
128Mb: x4, x8, x16
46/54
3.350
2.200
3.000
45.5/55.5
3.300
DDR SDRAM
2.163
2.950
t
RFC [MIN]) else
PRELIMINARY
©2001, Micron Technology, Inc.
45/55
3.250
t
2.125
DS and
2.900
IL
IL
t
(
DH
(
AC
DC
)
)