MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 15

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

AUTO REFRESH
of the DDR SDRAM and is analogous to CAS#-BE-
FORE-RAS# (CBR) REFRESH in FPM/EDO DRAMs.
This command is nonpersistent, so it must be issued
each time a refresh is required.
controller. This makes the address bits a “Don’t Care”
during an AUTO REFRESH command. The 128Mb
DDR SDRAM requires AUTO REFRESH cycles at an
average interval of 15.625µs (maximum).
switching between tasks, some flexibility in the abso-
lute refresh interval is provided. A maximum of eight
AUTO REFRESH commands can be posted to any
given DDR SDRAM, meaning that the maximum
absolute interval between any AUTO REFRESH
command and the next AUTO REFRESH command is
9 x 15.6µs (140.6µs). This maximum absolute interval
is to allow future support for DLL updates internal
to the DDR SDRAM to be restricted to AUTO
REFRESH cycles, without allowing excessive drift in
t
future functionality features, CKE must be active (High)
during the AUTO REFRESH period. The AUTO RE-
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
AC between updates.
AUTO REFRESH is used during normal operation
The addressing is generated by the internal refresh
To allow for improved efficiency in scheduling and
Although not a JEDEC requirement, to provide for
15
FRESH period begins when the AUTO REFRESH com-
mand is registered and ends
SELF REFRESH
data in the DDR SDRAM, even if the rest of the system
is powered down. When in the self refresh mode, the
DDR SDRAM retains data without external clocking.
The SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
The DLL is automatically disabled upon entering SELF
REFRESH and is automatically enabled upon exiting
SELF REFRESH (200 clock cycles must then occur before
a READ command can be issued). Input signals except
CKE are “Don’t Care” during SELF REFRESH.
sequence of commands. First, CK must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for
t
of any internal refresh in progress. A simple algorithm
for meeting both refresh and DLL requirements is to
apply NOPs for 200 clock cycles before applying any
other command.
XSNR because time is required for the completion
The SELF REFRESH command can be used to retain
The procedure for exiting self refresh requires a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb: x4, x8, x16
t
RFC later.
DDR SDRAM
PRELIMINARY
©2001, Micron Technology, Inc.