MT46V16M8TG-8L MICRON [Micron Technology], MT46V16M8TG-8L Datasheet - Page 35

• Manufacturer Part Number: MT46V16M8TG-8L
• Description: DOUBLE DATA RATE DDR SDRAM
• Manufacturer: MICRON [Micron Technology]

128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
COMMAND
ADDRESS
NOTE: 1. DI b = data-in for column b.
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
CK#
DM
DM
DM
DQ
DQ
DQ
CK
2. Subsequent element of data-in is applied in the programmed order following DI b.
3. An interrupted burst of 4 is shown; two data elements are written.
4. t WR is referenced from the first positive CK edge after the last data-in pair.
5. The PRECHARGE and WRITE commands are to the same bank.
6. A10 is LOW with the WRITE command (auto precharge is disabled).
7. DQS is required at T2 and T2n (nominal case) to register DM.
8. If the burst of 8 was used, DM would be required at T3 and T3n and not at T4 and T4n because the PRECHARGE
9. PRE = PRECHARGE command.
command would mask the last two data elements.
Bank a,
WRITE
Col b
T0
t
t
t
DQSS
DQSS
DQSS
DI
b
NOP
T1
DI
b
WRITE to Precharge – Interrupting
DI
b
T1n
NOP
T2
Figure 23
T2n
t
35
WR
T3
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
(a or all)
Bank,
T4
PRE
9
DON’T CARE
128Mb: x4, x8, x16
T5
NOP
DDR SDRAM
TRANSITIONING DATA
PRELIMINARY
t
RP
©2001, Micron Technology, Inc.
T6
NOP