S29CD016G SPANSION, S29CD016G Datasheet - Page 62

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

62
RY/BY#: Ready/Busy#
DQ6: Toggle Bit I
The device provides a RY/BY# open drain output pin as a way to indicate to the
host system that the Embedded Algorithms are either in progress or are com-
pleted. If the output is low, the device is busy with either a program, erase, or
reset operation. If the output is floating, the device is ready to accept any read/
write or erase operation. When the RY/BY# pin is low, the device does not accept
any additional program or erase commands with the exception of the Erase sus-
pend command. If the device enters Erase Suspend mode, the RY/BY# output is
floating. For programming, the RY/BY# is valid (RY/BY# = 0) after the rising edge
of the fourth WE# pulse in the four write pulse sequence. For chip erase, the RY/
BY# is valid after the rising edge of the sixth WE# pulse in the six write pulse
sequence. For sector erase, the RY/BY# is also valid after the rising edge of the
sixth WE# pulse.
If RESET# is asserted during a program or erase operation, the RY/BY# pin re-
mains a “0” (busy) until the internal reset operation is complete, which requires
a time of t
BY# to determine whether the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing (RY/BY# pin is “floating”),
the reset operation is completed in a time of t
rithms). The system can read data t
Since the RY/BY# pin is an open-drain output, several RY/BY# pins can be tied
together in parallel with a pull-up resistor to V
required to take RY/BY# to a V
Table 21 on page 65
Figure 19, on page
RY/BY# for read, reset, program, and erase operations, respectively.
Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is valid after the rising edge
of the final WE# pulse in the command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm operation, two immediately
consecutive read cycles to any address cause DQ6 to toggle. When the operation
is complete, DQ6 stops toggling. For asynchronous mode, either OE# or CE# can
be used to control the read cycles. For synchronous mode, the rising edge of
ADV# is used or the rising edge of clock while ADV# is Low.
After an erase command sequence is written, if all sectors selected for erasing
are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the Embedded Erase algo-
rithm erases the unprotected sectors, and ignores the selected sectors that are
protected.
The system can use DQ6 and DQ2 together to determine whether a sector is ac-
tively erasing or is erase-suspended. When the device is actively erasing (that is,
the Embedded Erase algorithm is in progress), DQ6 toggles. When the device en-
ters the Erase Suspend mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-
natively, the system can use DQ7 (see the subsection on
on page
60).
READY
(during Embedded Algorithms). The system can thus monitor RY/
75,
shows the outputs for RY/BY#.
Figure 21, on page 78
A d v a n c e
IH
level since the output is an open drain.
S29CD016G
RH
after the RESET# pin returns to V
I n f o r m a t i o n
READY
CC
and
. An external pull-up resistor is
Figure 23, on page 79
(not during Embedded Algo-
Figure 16, on page
“DQ7: Data# Polling”
S29CD016_00_A4 November 5, 2004
IH
shows
.
73,