S29CD016G SPANSION, S29CD016G Datasheet - Page 24

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

Notes:
1. Burst access starts with a rising CLK edge and when ADV# is active.
2. Configurations register 6 must be always set to 1 (CR6 = 1). Burst starts and data outputs on the rising CLK edge.
3. CR [13-10] = 0001 or three clock cycles
4. CR [13-10] = 0010 or four clock cycles
5. CR [13-10] = 0011 or five clock cycles
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DQ31-DQ0
DQ31-DQ0
DQ31-DQ0
Addresses
ADV#
Configuration Register
CLK
3
4
5
Burst CLK Edge Data Delivery
The device is capable of delivering data on either the rising or falling edge of CLK.
To deliver data on the rising edge of CLK, bit 6 in the Control Register (CR6) is
set to 1. The default configuration is set to the rising edge.
Burst Data Hold Control
The device is capable of holding data for one CLKs. The default configuration is
to hold data for one CLK and is the only valid state.
Asserting RESET# During A Burst Access
If RESET# is asserted low during a burst access, the burst access is immediately
terminated and the device defaults back to asynchronous read mode. Refer to
“RESET#: Hardware Reset Pin” on page 18
function.
The device contains a Configuration Register for configuring read accesses. The
Configuration Register is accessed by the Configuration Register Read and the
Configuration Register Write commands. The Configuration Register does not oc-
CR13
0
0
0
0
Valid Address
1st CLK
CR12
1
1
1
1
Table 8. Burst Initial Access Delay (Sheet 2 of 2)
Address 1 Latched
Three CLK Delay
CR11
2nd CLK
0
0
1
1
Four CLK Delay
Five CLK Delay
Figure 3. Burst Access Timing
A d v a n c e
CR10
0
1
0
1
3rd CLK
S29CD016G
D0
for more information on the RESET#
I n f o r m a t i o n
4th CLK
Initial Burst Access
D1
(CLK cycles)
D0
5th CLK
6
7
8
9
D2
D1
D0
S29CD016_00_A4 November 5, 2004
D2
D3
D1
D2
D4
D3