S29CD016G SPANSION, S29CD016G Datasheet - Page 59

• Manufacturer Part Number: S29CD016G
• Description: 16 Megabit (512 K x 32-Bit) CMOS 2.5 Volt-only Burst Mode / Dual Boot / Simultaneous Read/Write Flash Memory
• Manufacturer: SPANSION

November 5, 2004 S29CD016_00_A4
Legend:
DYB = Dynamic Protection Bit
OW = Address (A5–A0) is (011X10).
PPB = Persistent Protection Bit
PWA = Password Address. A0 selects between the low and high 32-bit
portions of the 64-bit Password
PWD = Password Data. Must be written over two cycles.
PL = Password Protection Mode Lock Address (A5–A0) is (001X10)
RD(0) = Read Data DQ0 protection indicator bit. If protected, DQ0=
1, if unprotected, DQ0 = 0.
RD(1) = Read Data DQ1 protection indicator bit. If protected, DQ1 =
1, if unprotected, DQ1 = 0.
Notes:
1.
2.
3.
4.
5.
6.
7.
Command (Notes)
Reset
SecSi Sector Entry
SecSi Sector Exit
SecSi Protection Bit Program
(5, 6)
SecSi Protection Bit Status
Password Program (5, 7, 8)
Password Verify
Password Unlock (7, 8)
PPB Program (5, 6)
All PPB Erase (5, 9, 10)
PPB Status (11, 12)
PPB Lock Bit Set
PPB Lock Bit Status
DYB Write (7)
DYB Erase (7)
DYB Status (12)
PPMLB Program (5,6)
PPMLB Status (5)
SPMLB Program (5, 6)
SPMLB Status (5)
See
All values are in hexadecimal.
Shaded cells in table denote read cycles. All other cycles are
write operations.
During unlock cycles, (lower address bits are 555 or 2AAh as
shown in table) address bits higher than A11 (except where BA
is required) and data bits higher than DQ7 are don’t cares.
The reset command returns the device to reading the array.
The fourth cycle programs the addressed locking bit. The fifth
and sixth cycles are used to validate whether the bit was fully
programmed. If DQ0 (in the sixth cycle) reads 0, the program
command must be issued and verified again.
Data is latched on the rising edge of WE#.
Table 1 on page 14
for description of bus operations.
Table 20. Sector Protection Command Definitions (x32 Mode)
A d v a n c e
1
3
4
6
6
4
4
5
6
6
4
3
4
4
4
4
6
6
6
6
Addr Data Addr Data
XXX
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
First
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
F0
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
2AA
Second
I n f o r m a t i o n
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
55
S29CD016G
SG+555
SA+555
Addr
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
555
Third
SA = Sector Address where security command applies. Address bits
A18:A11 uniquely select any sector.
SG = Sector Group Address
BA = Bank Address
SL = Persistent Protection Mode Lock Address (A5–A0) is (010X10)
WP = PPB Address (A5–A0) is (111010)
X = Don’t care
PPMLB = Password Protection Mode Locking Bit
SPMLB = Persistent Protection Mode Locking Bit
8.
9.
10. Before issuing the erase command, all PPBs should be
11. In the fourth cycle, 00h indicates PPB set; 01h indicates PPB not
12. The status of additional PPBs and DYBs may be read (following
Bus Cycles (Notes 1-4)
Data
The entire four bus-cycle sequence must be entered for each
portion of the password.
The fourth cycle erases all PPBs. The fifth and sixth cycles are
used to validate whether the bits were fully erased. If DQ0 (in
the sixth cycle) reads 1, the erase command must be issued and
verified again.
programmed in order to prevent over-erasure of PPBs.
set.
the fourth cycle) without reissuing the entire command
sequence.
88
90
60
60
38
C8
28
60
60
90
78
58
48
48
58
60
60
60
60
PWA[0-1] PWD[0-1]
PWA[0-1] PWD[0-1]
PWA[0-1] PWD[0-1]
SA+X02
SG+WP
Addr
OW
OW
WP
XX
SA
SA
SA
SA
SL
SL
PL
PL
Fourth
RD(0)
00/01
RD(1)
RD(0)
RD(0)
RD(0)
Data
00
68
68
60
X1
X0
68
68
SG+WP
Addr
OW
WP
SL
PL
Fifth
Data
48
48
40
48
48
SG+WP RD(0)
Addr
OW
WP
SL
PL
Sixth
RD(0)
RD(0)
RD(0)
RD(0)
Data
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