LTC2485 LINER [Linear Technology], LTC2485 Datasheet - Page 24

• Manufacturer Part Number: LTC2485
• Description: 24-Bit ?? ADC with Easy Drive Input Current Cancellation and I2C Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2485
Reference Current
In a similar fashion, the LTC2485 samples the differential
reference pins REF
of charge to and from the external driving circuits thus
producing a dynamic reference current. This current does
not change the converter offset, but it may degrade the
gain and INL performance. The effect of this current can be
analyzed in two distinct situations.
For relatively small values of the external reference capaci-
tors (C
settles almost completely and relatively large values for the
source impedance result in only small errors. Such values
for C
performance without significant benefits of reference filter-
ing and the user is advised to avoid them.
Larger values of reference capacitors (C
required as reference filters in certain configurations. Such
capacitors will average the reference sampling charge and
the external source resistance will see a quasi constant
reference differential impedance.
In the following discussion, it is assumed the input and
reference common mode are the same. Using internal
oscillator for 60Hz mode, the typical differential reference
resistance is 1MΩ which generates a full-scale (V
gain error of 0.51ppm for each ohm of source resistance
driving the REF
related difference resistance is 1.1MΩ and the resulting full-
scale error is 0.46ppm for each ohm of source resistance
driving the REF
difference resistance is 1.2MΩ and the resulting full-scale
error is 0.42ppm for each ohm of source resistance driving
the REF
external oscillator with a frequency f
sion clock operation), the typical differential reference resis-
tance is 0.30 • 10
resistance driving the REF
• 10
for various combinations of source resis-tance seen by the
REF
that pin are shown in Figures 16-19.
In addition to this gain error, the converter INL perfor-
mance is degraded by the reference source impedance.
The INL is caused by the input dependent terms
24
–6
+
REF
or REF
• f
REF
+
EOSC
will deteriorate the converter offset and gain
and REF
< 1nF), the voltage on the sampling capacitor
–
ppm gain error. The typical +FS and –FS errors
pins and external capacitance connected to
+
+
and REF
or REF
–
+
U
12
and REF
pins. When CA0/F
/f
EOSC
–
–
U
+
pins. For 50Hz mode, the related
pins. For 50Hz/60Hz mode, the
or REF
Ω and each ohm of source
–
transferring small amount
–
W
EOSC
pins will result in 1.67
REF
0
(external conver-
is driven by an
> 1nF) may be
U
REF
/2)
–V
pin current as expressed in Figure 12. When using internal
oscillator and 60Hz mode, every 100Ω of reference source
resistance translates into about 0.67ppm additional INL
error. When using internal oscillator and 50Hz/60Hz mode,
every 100Ω of reference source resistance translates into
about 0.61ppm additional INL error. When using internal
oscillator and 50Hz mode, every 100Ω of reference source
resistance translates into about 0.56ppm additional INL
error. When CA0/F
a frequency f
ing REF
f
cal INL error due to the source resistance driving the REF
or REF
advised to minimize the source impedance driving the
REF
In applications where the reference and input common
mode voltages are different, extra errors are introduced.
For every 1V of the reference and input common mode
voltage difference (V
each Ohm of reference source resistance introduces an
extra (V
which is 0.074ppm when using internal oscillator and
60Hz mode. When using internal oscillator and 50Hz/60Hz
mode, the extra full-scale gain error is 0.067ppm. When
using internal oscillator and 50Hz mode, the extra gain
error is 0.061ppm. If an external clock is used, the corre-
sponding extra gain error is 0.24 • 10
The magnitude of the dynamic reference current depends
upon the size of the very stable internal sampling capaci-
tors and upon the accuracy of the converter sampling
clock. The accuracy of the internal clock over the entire
temperature and power supply range is typically better
than 0.5%. Such a specification can also be easily achieved
by an external clock. When relatively stable resistors
(50ppm/°C) are used for the external source impedance
seen by V
current gain error will be insignificant (about 1% of its
value over the entire temperature and voltage range). Even
for the most stringent applications a one-time calibration
operation may be sufficient.
In addition to the reference sampling charge, the reference pins
ESD protection diodes have a temperature dependent leakage
EOSC
IN
+
2
ppm additional INL error. Figure 20 shows the typi-
/(V
and REF
–
REFCM
pins when large C
+
REF
REF
or REF
• R
+
EOSC
–
and V
– V
EQ
pins.
) – (0.5 • V
, every 100Ω of source resistance driv-
–
INCM
0
REF
is driven by an external oscillator with
translates into about 2.18 • 10
REFCM
)/(V
–
, the expected drift of the dynamic
REF
REF
– V
REF
values are used. The user is
• R
INCM
• D
EQ
T
) full-scale gain error,
)/R
) and a 5V reference,
–6
EQ
• f
in the reference
EOSC
ppm.
–6
2485fa
+
•