LTC2485 LINER [Linear Technology], LTC2485 Datasheet - Page 15

• Manufacturer Part Number: LTC2485
• Description: 24-Bit ?? ADC with Easy Drive Input Current Cancellation and I2C Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Rejection Mode (FA, FB)
The LTC2485 includes a high accuracy on-chip oscillator
with no required external components. Coupled with a 4th
order digital lowpass filter, the LTC2485 rejects line fre-
quency noise. In the default mode, the LTC2485 simulta-
neously rejects 50Hz and 60Hz by at least 87dB. The
LTC2485 can also be configured to selectively reject 50Hz
or 60Hz to better than 110dB.
Speed Mode (SPD)
The LTC2485 continuously performs offset calibrations.
Every conversion cycle, two conversions are automati-
cally performed (default) and the results combined. This
result is free from offset and drift. In applications where
the offset is not critical, the autocalibration feature can be
disabled with the benefit of twice the output rate.
Linearity, full-scale accuracy and full-scale drift are iden-
tical for both 2x and 1x speed modes. In both the 1x and
2x speed there is no latency. This enables input steps or
multiplexer channel changes to settle in a single conversion
cycle easing system overhead and increasing the effective
conversion rate.
LTC2485 Data Format
After a START condition, the master sends a 7-bit address
followed by a R/W bit. The bit R/W is 1 for a Read request
and 0 for a Write request. If the 7-bit address agrees with
an LTC2485’s address, that device is selected. When the
device is in the conversion state, it does not accept the
Table 3. LTC2485 Output Data Format
DIFFERENTIAL INPUT VOLTAGE
V
V
FS** – 1LSB
0.5 • FS**
0.5 • FS** – 1LSB
0
–1LSB
– 0.5 • FS**
– 0.5 • FS** – 1LSB
– FS**
V
*The differential input voltage V
IN
IN
IN
*
* ≥ FS**
* < –FS**
U
U
IN
= IN
W
+
BIT 31
– IN
SIG
1
1
1
1
1
0
0
0
0
0
–
. **The full-scale voltage FS = 0.5 • V
U
BIT 30
MSB
1
0
0
0
0
1
1
1
1
0
BIT 29
Table 2. LTC2485 Status Bits
INPUT RANGE
V
0V ≤ V
–0.5 • V
V
request and issues a Not-Acknowledge (NAK) by leaving
SDA HIGH. A write operation will also generate an NAK
signal. If the conversion is complete, it issues an acknowl-
edge (ACK) by pulling SDA LOW.
The LTC2485 has two registers. The output register
contains the result of the last conversion and a user
programmable configuration register that sets the con-
verter operation mode.
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1µA. When the LTC2485 is addressed for a
Read operation, it acknowledges (by pulling SDA LOW)
and acts as a transmitter. The master and receiver can read
up to four bytes from the LTC2485. After a complete Read
operation (4 bytes), the output register is emptied, a new
conversion is initiated, and a following Read request in the
same output phase will be NAKed. The LTC2485 output
data stream is 32 bits long, shifted out on the falling edges
of SCL. The first bit is the conversion result sign bit (SIG),
(see Tables 2 and 3). This bit is HIGH if V
if V
IN
IN
0
1
1
0
0
1
1
0
0
1
≥ 0.5 • V
< – 0.5 • V
IN
IN
<0. The second bit is the most significant bit (MSB)
REF
< 0.5 • V
≤ V
REF
REF
BIT 28
REF
IN
0
1
0
1
0
1
0
1
0
1
.
REF
< 0V
BIT 27
0
1
0
1
0
1
0
1
0
1
…
…
…
…
…
…
…
…
…
…
…
BIT 31
SIG
1
1
0
0
IN
LTC2485
BIT 0
0
1
0
1
0
1
0
1
0
1
≥ 0. It is LOW
BIT 30
MSB
15
1
0
1
0
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