LTC2485 LINER [Linear Technology], LTC2485 Datasheet - Page 11

• Manufacturer Part Number: LTC2485
• Description: 24-Bit ?? ADC with Easy Drive Input Current Cancellation and I2C Interface
• Manufacturer: LINER [Linear Technology]

PI FU CTIO S
REF
The voltage on these pins can have any value between GND
and V
more positive than the reference negative input, REF
at least 0.1V.
V
(Pin 8) with a 1µF tantalum capacitor in parallel with 0.1µF
ceramic capacitor as close to the part as possible.
IN
voltage on these pins can have any value between
GND – 0.3V and V
converter bipolar input range (V
from –0.5 • V
the converter produces unique overrange and underrange
output codes.
SCL (Pin 6): Serial Clock Pin of the I
LTC2485 can only act as a slave and the SCL pin only
accepts external serial clock. Data is shifted into the SDA
pin on the rising edges of the SCL clock and output
through the SDA pin on the falling edges of the
SCL clock.
FU CTIO AL BLOCK DIAGRA
CC
+
U
(Pin 4), IN
U
+
(Pin 2): Positive Supply Voltage. Bypass to GND
(Pin 1), REF
CC
as long as the reference positive input, REF
U
REF
U
–
(Pin 5): Differential Analog Input. The
to 0.5 • V
–
U
(Pin 3): Differential Reference Input.
CC
1
4
5
+ 0.3V. Within these limits the
REF
IN
IN
+
–
+
REF
SENSOR
TEMP
. Outside this input range
IN
= IN
MUX
2
+
C Interface. The
– IN
–
) extends
W
3
REF
–
IN
IN
+
, by
–
, is
+
–
AUTOCALIBRATION
REF
3RD ORDER
AND CONTROL
∆Σ ADC
–
REF
SDA (Pin 7): Bidirectional Serial Data Line of the I
Interface. In the transmitter mode (Read), the conversion
result is output through the SDA pin, while in the receiver
mode (Write), the device configuration bits are input
through the SDA pin. At data input mode, the pin is high
impedance; while at data output mode, it is an open-drain
N-channel driver and therefore an external pull-up resistor
or current source to V
GND (Pin 8): Ground. Connect this pin to a ground plane
through a low impedance connection.
CA1 (Pin 9): Chip Address Control Pin. The CA1 pin is
configured as a three state (LOW, HIGH, or Floating)
address control bit for the device I
CA0/F
Input Pin. When no transition is detected on the CA0/F
pin, it is a two state (HIGH or Floating) address control bit
for the device I
external clock signal with a frequency f
10kHz, the converter uses this signal as its system clock
and the fundamental digital filter rejection null is located at
a frequency f
internally to a HIGH.
+
0
(Pin 10): Chip Address Control Pin/External Clock
V
2
CC
8
GND
EOSC
INTERFACE
2
C address. When the pin is driven by an
SERIAL
I
OSCILLATOR
/5120 and sets the Chip Address CA0
2
INTERNAL
C
CC
is needed.
CA0/F
SDA
SCL
CA1
0
2485 FB
10
6
7
9
2
C address.
LTC2485
EOSC
of at least
11
2485fa
2
C
0