LTC2485 LINER [Linear Technology], LTC2485 Datasheet - Page 16

• Manufacturer Part Number: LTC2485
• Description: 24-Bit ?? ADC with Easy Drive Input Current Cancellation and I2C Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
LTC2485
of the result. The first two bits (SIG and MSB) can be used
to indicate over range conditions. If both bits are HIGH, the
differential input voltage is above +FS and the following 24
bits are set to LOW to indicate an overrange condition. If
both bits are LOW, the input voltage is below –FS and the
following 24 bits are set to HIGH to indicate an underrange
condition. The function of these two bits is summarized in
Table 1. The next 24 bits contain the conversion results in
binary two’s complement format. The remaining six bits
are Sub LSBs below the 24-bit level.
As long as the voltage on the IN
tained within the – 0.3V to (V
operating range, a conversion result is generated for any
differential input voltage V
+FS=0.5 • V
+FS, the conversion result is clamped to the value corre-
sponding to the +FS + 1LSB. For differential input voltages
below –FS, the conversion result is clamped to the value
corresponding to –FS – 1LSB.
Initiating a New Conversion
When the LTC2485 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device
is ready for a Read operation. After the device acknowl-
edges a Read request, the device exits the sleep state and
enters the data output state. The data output state con-
16
START BY
MASTER
REF
. For differential input voltages greater than
ADDRESS
1
7-BIT
U
…
7
SLEEP
U
IN
CC
from –FS = –0.5 • V
+ 0.3V) absolute maximum
8
R
LTC2485
ACK BY
+
Figure 4. Timing Diagram for Reading from the LTC2485
W
and IN
9
SGN
–
1
pins is main-
U
MSB
2
REF
…
D23
to
MASTER
ACK BY
9
cludes and the LTC2485 starts a new conversion once a
STOP condition is issued by the master or all 32 bits of data
are read out of the device.
During the data read cycle, a stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This stop command must be
issued during the ninth clock cycle of a byte read when the
bus is free (the ACK/NAK cycle).
LTC2485 Address
The LTC2485 has two address pins, enabling one in 6
possible addresses, as shown in Table 4.
Table 4. LTC2485 Address Assignment
* CA0/F
In addition to the configurable addresses listed in Table 5,
the LTC2485 also contains a global address (1110111)
which may be used for synchronizing multiple LTC2485s.
1
DATA OUTPUT
0
CA1
LOW
LOW
Floating
Floating
HIGH
HIGH
is treated as HIGH when driven by a valid external clock.
LSB
2
3
4
CA0/F
HIGH
Floating
HIGH
Floating
HIGH
Floating
SUB LSBs
5
0
*
6
7
Address
001 01 00
001 01 01
001 01 11
010 01 00
010 01 10
010 01 11
MASTER
8
NAK BY
9
2485 F04
2485fa