LTC2485 LINER [Linear Technology], LTC2485 Datasheet - Page 12

• Manufacturer Part Number: LTC2485
• Description: 24-Bit ?? ADC with Easy Drive Input Current Cancellation and I2C Interface
• Manufacturer: LINER [Linear Technology]

APPLICATIO S I FOR ATIO
Initially, the LTC2485 performs a conversion. Once the
conversion is complete, the device enters the sleep state.
While in this sleep state, power consumption is reduced
by two orders of magnitude. The part remains in the sleep
state as long as it is not addressed for a read/write
operation. The conversion result is held indefinitely in a
static shift register while the converter is in the sleep state.
The device will not acknowledge an external request
during the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once the
LTC2485
12
CONVERTER OPERATION
Converter Operation Cycle
The LTC2485 is a low power, ∆Σ analog-to-digital con-
verter with an I
operation is made up of three states. The converter
operating cycle begins with the conversion, followed by
the low power sleep state and ends with the data output/
input (see Figure 1).
Figure 1. LTC2485 State Transition Diagram
2
C interface. After power on reset, its
U
DEFAULT CONFIGURATION:
NO
NO
1X SPEED, AUTOCAL
50/60Hz REJECTION
POWER ON RESET
EXTERNAL INPUT
ACKNOWLEDGE
DATA OUTPUT
CONVERSION
U
OR READ
32-BITS
SLEEP
STOP
YES
YES
2485 F01
W
U
LTC2485 is addressed for a read operation, the device
begins outputting the conversion result under control of
the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 32 bits long and contains a
24-bit plus sign conversion result. This result is shifted
out on the SDA pin under the control of the SCL. Data is
updated on the falling edges of SCL allowing the user to
reliably latch data on the rising edge of SCL. In write
operation, the device accepts one configuration byte and
the data is shifted in on the rising edges of the SCL. A new
conversion is initiated by a STOP condition following a
valid write operation or at the conclusion of a data read
operation (read out all 32 bits).
I
The LTC2485 communicates through an I
The I
porting multiple devices and masters on a single bus. The
connected devices can only pull the bus wires LOW and
they never drive the bus HIGH. The bus wires are exter-
nally connected to a positive supply voltage via a current-
source or pull-up resistor. When the bus is free, both
lines are HIGH. Data on the I
rates of up to 100kbit/s in the Standard-mode and up to
400kbit/s in the Fast-mode.
Each device on the I
address stored in that device and can operate as either a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when per-
forming data transfers. A master is the device which
initiates a data transfer on the bus and generates the clock
signals to permit that transfer. At the same time any device
addressed is considered a slave.
The LTC2485 can only be addressed as a slave. Once
addressed, it can receive configuration bits or transmit the
last conversion result. Therefore the serial clock line SCL
is an input only and the data line SDA is bidirectional. The
device supports the Standard-mode and the Fast-mode
for data transfer speeds up to 400kbit/s. Figure 2 shows
the definition of timing for Fast/Standard-mode devices
on the I
2
C INTERFACE
2
C interface is a 2-wire open-drain interface sup-
2
C-bus.
2
C bus is recognized by a unique
2
C-bus can be transferred at
2
C interface.
2485fa