AS1545_1 AMSCO [austriamicrosystems AG], AS1545_1 Datasheet - Page 28

• Manufacturer Part Number: AS1545_1
• Description: Dual, 12-Bit, 1MSPS, SAR ADC
• Manufacturer: AMSCO [austriamicrosystems AG]

AS1545
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
Power vs. Throughput Rate
The power consumption of the AS1545 varies with throughput rate. When using very slow throughput rates and as fast
an SCLK frequency as possible, the various power-down options can be used to make significant power savings.
However, the AS1545 quiescent current is low enough that even without using the power-down options, there is a
noticeable variation in power consumption with sampling rate. This is true whether a fixed SCLK value is used or if it is
scaled with the sampling rate.
normal mode for a fixed maximum SCLK frequency, and an SCLK frequency that scales with the sampling rate with
V
Serial Interface
The timing diagram for serial interfacing to the AS1545 is shown in
clock and controls the transfer of information from the AS1545 during conversion.
The CSN signal initiates the data transfer and conversion process. The falling edge of CSN puts the track-and-hold
into hold mode, at which point the analog input is sampled and the bus is taken out of three-state. The conversion is
also initiated at this point and requires a minimum of 15 SCLKs to complete. Once 13 SCLK falling edges have
elapsed, the track-and-hold goes back into track on the next SCLK rising edge, as shown in
16-SCLK transfer is used, then two trailing zeros will appear after the final LSB. On the rising edge of CSN, the
conversion is terminated and D
low for a further 15 SCLK cycles on D
zero).
Likewise, if CSN is held low for a further 15 SCLK cycles on D
This is illustrated in
three-state on the 32nd SCLK falling edge or the rising edge of CSN, whichever occurs first.
A minimum of 15 serial clock cycles are required to perform the conversion process and to access data from one
conversion on either data line of the AS1545. CSN going low provides the 3 leading zeros to be read in by the
microcontroller or DSP. The remaining data is then clocked out by subsequent SCLK falling edges. Therefore, the first
falling clock edge on the serial clock has the leading zero provided and also clocks out the second leading zero. The
12-bit result then follows after a third leading zero with the final bit in the data transfer valid on the 15th falling edge,
having being clocked out on the previous (14th) falling edge. It may also be possible to read in data on each SCLK
rising edge depending on the SCLK frequency or the supply voltage. The secondrising edge of SCLK after the CSN
falling edge would have the third leading zero provided, and the 14th rising SCLK edge would have DB0 provided.
If a falling edge of SCLK is coincident with the falling edge of CSN, then this falling edge of SCLK is not acknowledged
by the AS1545, and the next falling edge of SCLK will be the first registered after the falling edge of CSN.
Figure 51. Timing Diagram
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DD
= 3V and V
DOUTA
DOUTB
SCLK
CSN
THREE-
t
DD
STATE
CSS
= 5V, respectively. In all cases, the internal reference was used.
Figure 52
3 LEADING ZEROES
0
t
1
CSDOE
0
where the case for D
Figure 10 on page 11
OUT
2
0
A and D
OUT
3
DB11
A, the data from Conversion B is output on D
OUT
4
DB10
B go back into three-state. If CSN is not brought high but is instead held
t
t
DOV
CH
OUT
5
t
shows plots of power vs. the throughput rate when operating in
DOH
Revision 1.01
DB9
A is shown. In this case, the D
OUT
B, the data from Conversion A is output on D
Figure
DB2
t
CL
51. The serial clock provides the conversion
DB1
14
t
CSDOD
B
DB0
OUT
OUT
line in use goes back into
THREE-STATE
A (followed by 1 trailing
Figure 51
t
QUIET
t
CSPW
at Point B. If a
OUT
28 - 34
B.