AS1545_1 AMSCO [austriamicrosystems AG], AS1545_1 Datasheet - Page 16

• Manufacturer Part Number: AS1545_1
• Description: Dual, 12-Bit, 1MSPS, SAR ADC
• Manufacturer: AMSCO [austriamicrosystems AG]

AS1545
Datasheet - Te r m i n o l o g y
Zero Code Error
The Zero Code Error is the deviation of the midscale transition (all 0xFFFh to all 0x000h in 2’s complement output
coding) from the ideal input voltage (V
Zero Code Error =
Zero Code Error Match
The Zero Code Error Match defines the maximum deviation of the Zero Code Errors across all 6 channels of V
Fully Differential Mode (2’s complement output coding).
Positive Gain Error
The Positive Gain Error is the deviation last code transition (0x7FEh) to (0x7FFh) in 2’s complement output coding
from the ideal input voltage (V
Differential Mode.
Positive Gain Error =Zero Code Error –
Negative Gain Error
The Negative Gain Error is the deviation first code transition (0x800h) to (0xFFFh) in 2’s complement output coding
from the ideal input voltage (V
Differential Mode.
Negative Gain Error =
Positive / Negative Gain Error Match
The Positive / Negative Gain Error Match defines the maximum deviation of the Positive / Negative Gain Errors across
all 6 channels of V
Signal-to-Noise Plus Distortion (SINAD)
The Signal to Noise Plus Distortion Ratio defines the ratio between the RMS value of the fundamental (input signal)
and the equivalent RMS value of all other spectral components below one-half the sampling frequency, including
harmonics but excluding DC. SINAD will be equal to SNR in an distortion free ADC.
Effective Number of Bits (ENOB)
The Effective Number of Bits indicates the actual resolution of the converter. The ENOB can be calculated from the
Signal to Noise Plus Distortion Ratio (SINAD).
ENOB =
Signal-to-Noise Ratio (SNR)
The Signal to Noise Ratio defines the ratio between the RMS value of the fundamental (input signal) to the RMS value
of the sum of all other spectral components below one-half of the sampling frequency, excluding harmonics and DC.
The theoretical SNR for an ideal N bit ADC is limited by the quantization error and is described by the formula:
SNR = 6.02*N +1.76 (dB)
Therefore, for a 12-bit ADC, the maximum SNR is 74dB.
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SINAD 1,76
----------------------------------
6,02
–
IN
VINP VINN
---------------------------------- -
in Fully Differential Mode (2’s complement output coding).
⎧
⎨
⎩
VREF
VINP VINN
---------------------------------- -
–
VREF
IN +
IN +
–
- V
- V
×
IN -
IN -
4096
IN +
= +V
= -V
⎧
⎨
⎩
×
- V
VINP VINN
---------------------------------- -
4096
+
REF
REF
IN -
2048
VREF
= 0V) in Fully Differential Mode.
+ 0.5LSB @ Range=1 and -V
- 0.5LSB @ Range=1 and +V
+
–
2048
–
Revision 1.01
AVG MeasuredCodes
–
×
AVG MeasuredCodes
(
4096
(
+
2048
–
AVG MeasuredCodes
REF
REF
)
/2 + 0.5LSB @ Range=0) in Fully
/2 - 0.5LSB @ Range=0) in Fully
(
)
⎫
⎬
⎭
–
ZeroCodeError
)
⎫
⎬
⎭
IN
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in