AS1545_1 AMSCO [austriamicrosystems AG], AS1545_1 Datasheet - Page 25

• Manufacturer Part Number: AS1545_1
• Description: Dual, 12-Bit, 1MSPS, SAR ADC
• Manufacturer: AMSCO [austriamicrosystems AG]

AS1545
Datasheet - A p p l i c a t i o n I n f o r m a t i o n
10 Application Information
Operation Modes
The operation mode of the AS1545 is selected by controlling the (logic) state of the CSN signal during a conversion
process. There are three possible modes of operation: Full Power-UP mode, Full Power-Down mode, and Partial
Power-Down mode. After a conversion is initiated, the point at which CSN is pulled high determines which power-down
mode, if any, the device enters. Similarly, in power-down mode, CSN can control whether the device returns to Full
Power-Up mode or remains in power-down. These modes of operation provides flexible power management and can
be selected to optimize the power dissipation/throughput rate ratio for differing application requirements.
Full Power-Up Mode
In this mode the AS1545 is fully powered all the time without any power-up time. This mode is suitable for applications
that need the fastest throughput rates.
mode. On the falling edge of CSN conversion is initiated. To ensure that the part remains fully powered up at all times,
CSN must remain low until at least 10 SCLK falling edges have elapsed after the falling edge of CSN. The conversion
is terminated and D
falling edge but before the 15th SCLK falling edge. During this process the part remains powered up.
Figure 46. Full Power-Up Mode Operation
Fiveteen serial clock cycles are required to complete the conversion and access the conversion result. The D
does not return to three-state after 15 SCLK cycles have elapsed, but instead does so when CSN is brought high
again. If CSN is left low for another SCLK cycle (for example, if only a 16 SCLK burst is available), one trailing zeros
are clocked out after the data. If CSN is left low for a further 16 SCLK cycles, the result from the other ADC on board is
also accessed on the same D
Once 32 SCLK cycles have elapsed, the D
brought high prior to this, the D
and D
by bringing CSN low again (assuming the required acquisition time is allowed).
Full Power-Down Mode
This mode is intended for applications where throughput rates are slower. In this mode the AS1545 will stay power
down until the falling edge of CSN. The device continues to power-up when the CSN is held low till the falling edge of
the 10th SCLK.
When the AS1545 is in full power-down, all analog circuitry is powered down. Full power-down is entered in a similar
way as partial power-down, except the timing sequence shown in
process must be interrupted in a similar fashion by bringing CSN high anywhere after the second falling edge of SCLK
and before the 10th falling edge of SCLK. The device enters partial power-down at this point. To reach full power-
down, the next conversion cycle must be interrupted in the same way, as shown in
high in this window of SCLKs, the part completely powers down.
Note: It is important to note, that the full power-down mode can only be established if both digital outputs, D
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OUT
D
D
D
SCLK
CSN
OUT
OUT
OUT
B have returned to three-state, another conversion can be initiated after the quiet time, t
A
B
B are not left floating. Therefore a pulldown or pullup of >1GΩ is required.
OUT
A and D
OUT
OUT
OUT
1
line, as shown in
line returns to three-state at that point. Once a data transfer is complete and D
B go back into three-state, if CSN is brought high any time after the 10th SCLK
3 LEADING ZEROS + CONVERSION RESULT 12bits
Figure 46
OUT
line returns to three-state on the 32nd SCLK falling edge. If CSN is
shows the general diagram of the operation of the AS1545 in this
Figure 52 (see Serial Interface on page 28)
Revision 1.01
Figure 50
10
must be executed twice. The conversion
Figure
48. Once CSN is brought
15
QUIET
, has elapsed
OUT
OUT
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A and
OUT
line
A