AS1545_1 AMSCO [austriamicrosystems AG], AS1545_1 Datasheet - Page 18

• Manufacturer Part Number: AS1545_1
• Description: Dual, 12-Bit, 1MSPS, SAR ADC
• Manufacturer: AMSCO [austriamicrosystems AG]

AS1545
Datasheet - D e t a i l e d D e s c r i p t i o n
9 Detailed Description
The AS1545 is a dual, 6-channel (six single-ended, three pseudo-differential or three fully-differential for each
multiplexer), 12-bit, 1 MSPS, high speed, successive approximation (SAR) analog-to-digital converter (ADC). The
AS1545 is designed to operate with a single +2.7V to +5.25V supply and a sampling rate of up to 1 MSPS. The serial
interface provides easy interfacing to microprocessors.
The AS1545 feature two on-chip, differential track-and-hold amplifiers, two successive approximation ADCs, and a
serial interface with two separate data output pins on a single die. The AS1545 is available in a 32-lead TQFN
package, offering the user considerable space-saving advantage.
The AS1545 can convert analog input signals in the range [0V to V
pseudo-differential mode or [-V
an on-chip 2.5V reference that can be overdriven when an external reference is preferred. If the internal reference is to
be used then the output needs to be buffered first. The AS1545 also features power-down options to allow power
saving between conversions. The power-down feature is implemented via the standard serial interface.
Analog Input
The AS1545 consists of successive approximation ADCs, each around two capacitive DACs and 12 analog inputs.
Each on-board ADC has six analog inputs that can be configured as six single-ended channels, three pseudo
differential channels, or three fully differential channels.
acquisition and conversion phase, respectively. The ADC consists of a control logic, a SAR, and two capacitive DACs.
Figure 32. ADC Acquisition
Acquisition Time
During data acquisition time (t
balanced condition, and the sampling capacitor arrays acquire the differential signal on the input. At the raising edge of
the CSN signal, SW3 opens and SW1 and SW2 go into hold position, causing the comparator to become unbalanced.
Both inputs are disconnected once the conversion begins. The control logic and the charge redistribution DACs are
used to add and subtract fixed amounts of charge from the sampling capacitor arrays to bring the comparator back into
a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the
ADC output code. The output impedances of the sources driving the AIN+ and AIN- pins must be matched. Otherwise,
the two inputs will have different settling times, resulting in errors.
Figure 33. ADC Conversion Phase
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Analog Input
Multiplexer
CH0
CH1
CH2
CH3
CH4
CH5
Analog Input
Multiplexer
CH0
CH1
CH2
CH3
CH4
CH5
ACQ
REFIN
) SW3 is closed, SW1 and SW2 are in track position, the comparator is held in a
/2 to +V
AIN+
AIN-
AIN+
AIN-
REFIN
B
A
A
B
VREF
/2] or [-V
A
B
B
A
VREF
SW1
SW2
SW1
SW2
Revision 1.01
11pF
11pF
C
Figure 32
C
C
SWITCH
C
S
S
11pF
11pF
REFIN
C
C
SWITCH
S
S
R
R
IN
IN
R
R
includes all parasitics
IN
IN
to +V
includes all parasitics
and
REFIN
SW3
REFIN
Figure 33
SW3
] or [0V to 2 x V
COMPARATOR
] in fully differential mode. The AS1545 has
COMPARATOR
+
-
+
-
shows one of these ADCs in
REFIN
CAPACITIVE
CAPACITIVE
CONTROL
CAPACITIVE
CAPACITIVE
LOGIC
DAC
DAC
CONTROL
] in single-ended or
LOGIC
DAC
DAC
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