bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 79

• Manufacturer Part Number: bc41b143a07
• Description: Single Chip Bluetooth
• Manufacturer: ETC-unknow

PCM_CLK and PCM_SYNC Generation
BlueCore4-ROM has two methods of generating PCM_CLK and PCM_SYNC in master mode. The first is generating
these signals by Direct Digital Synthesis (DDS) from BlueCore4-ROM internal 4MHz clock (which is used in
BlueCore2-External). Using this mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz. The second
is generating PCM_CLK and PCM_SYNC by DDS from an internal 48MHz clock (which allows a greater range of
frequencies to be generated with low jitter but consumes more power). This second method is selected by setting bit
48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of
PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in
PSKEY_PCM_CONFIG32.
The Equation 9.11 describes PCM_CLK frequency when being generated using the internal 48MHz clock:
The frequency of PCM_SYNC relative to PCM_CLK can be set using Equation 9.12:
CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to
generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to
0x08080177.
9.7.9
The PCM configuration is set using two PS Keys, PSKEY_PCM_CONFIG32 detailed in Table 9.11 and
PSKEY_PCM_LOW_JITTER_CONFIG in Table 9.12. The default for PSKEY_PCM_CONFIG32 is 0x00800000, i.e.,
first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating 256kHz
PCM_CLK from 4MHz internal clock with no tri-state of PCM_OUT.
CS-101564-DSP12
PCM_SYNC
Equation 9.11: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock
PCM_OUT
PCM_CLK
PCM Configuration
PCM_IN
t
susclksynch
Equation 9.12: PCM_SYNC Frequency Relative to PCM_CLK
Figure 9.26: PCM Slave Timing Short Frame Sync
t
hsclksynch
t
supinsclkl
t
sclkh
t
dsclkhpout
MSB (LSB)
MSB (LSB)
f
Production Information
=
f
© CSR plc 2003-2007
f
CNT
sclk
CNT
=
SYNC
t
hpinsclkl
t
tsclkl
PCM
_
_
RATE
LIMIT
_
_
LIMIT
CLK
×
24
×
MHz
8
LSB (MSB)
t
r
LSB (MSB)
,t
f
Device Terminal Descriptions
t
dpoutz
t
dpoutz
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