bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 51

• Manufacturer Part Number: bc41b143a07
• Description: Single Chip Bluetooth
• Manufacturer: ETC-unknow

9.1.4
TXRX_PIO_CONTROL (0x209) is used to control external RF components such as a switch, an external PA or an
external LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this purpose, as Table 9.1 indicates.
9.2
The BlueCore4-ROM RF local oscillator and internal digital clocks are derived from the reference clock at the
BlueCore4-ROM XTAL_IN input. This reference may be either an external clock or from a crystal connected between
XTAL_IN and XTAL_OUT. The crystal mode is described in section 9.3.
9.2.1
BlueCore4-ROM can be configured to accept an external reference clock from another device (such as TCXO) at
XTAL_IN by connecting XTAL_OUT to ground. The external clock can be either a digital level square wave or
sinusoidal, and this may be directly coupled to XTAL_IN without the need for additional components. If the peaks of
the reference clock are below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor
(approximately 33pF) connected to XTAL_IN. A digital level reference clock gives superior noise immunity, as the high
slew rate clock edges have lower voltage to phase conversion.
The external clock signal should meet the specifications in Table 9.2:
9.2.2
The impedance of the XTAL_IN will not change significantly between operating modes, typically 10fF. When
transitioning from Deep Sleep to an active state a spike of up to 1pC may be measured. For this reason it is
recommended that a buffered clock input be used.
CS-101564-DSP12
Frequency
Duty cycle
Edge Jitter (At Zero Crossing)
Signal Level
TXRX_PIO_CONTROL Value
(a)
(b)
(c)
The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies
VDD_ANA is 1.8V nominal
If the external clock is driven through a DC blocking capacitor, then maximum allowable amplitude is reduced from
VDD_ANA to 800mV pk-pk
Control of External RF Components
External Reference Clock Input (XTAL_IN)
External Mode
XTAL_IN Impedance in External Mode
(a)
0
1
2
3
4
Table 9.2: External Clock Specifications
Table 9.1: TXRX_PIO_CONTROL Values
AUX_DAC Use
PIO[0], PIO[1], AUX_DAC not used to control RF. Power ramping is internal.
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC not used.
Power ramping is internal.
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
gain of external PA. Power ramping is external.
PIO[0] is low during RX, PIO[1] is low during TX. AUX_DAC used to set gain
of external PA. Power ramping is external.
PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set
gain of external PA. Power ramping is internal.
Production Information
© CSR plc 2003-2007
400mV pk-pk
7.5MHz
20:80
Min
-
16MHz
50:50
Typ
-
-
Device Terminal Descriptions
VDD_ANA
15ps rms
40MHz
80:20
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Max
(b) (c)