bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 69

• Manufacturer Part Number: bc41b143a07
• Description: Single Chip Bluetooth
• Manufacturer: ETC-unknow

9.6
BlueCore4-ROM uses 16-bit data and 16-bit address serial peripheral interface, where transactions may occur when
the internal processor is running or is stopped. This section details the considerations required when interfacing to
BlueCore4-ROM via the four dedicated serial peripheral interface terminals. Data may be written or read one word at
a time or the auto increment feature may be used to access blocks.
9.6.1
The BlueCore4-ROM is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table 9.8
shows the instruction cycle for an SPI transaction.
With the exception of reset,SPI_CSB must be held low during the transaction. Data on SPI_MOSI is clocked into the
BlueCore4-ROM on the rising edge of the clock line SPI_CLK. When reading, BlueCore4-ROM will reply to the master
on SPI_MISO with the data changing on the falling edge of the SPI_CLK. The master provides the clock on SPI_CLK.
The transaction is terminated by taking SPI_CSB high.
Sending a command word and the address of a register for every time it is to be read or written is a significant
overhead, especially when large amounts of data are to be transferred. To overcome this BlueCore4-ROM offers
increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CSB is kept low,
which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read.
CS-101564-DSP12
1
2
3
4
5
Reset the SPI interface
Write the command word
Write the address
Write or read data words
Termination
Serial Peripheral Interface
Instruction Cycle
Table 9.8: Instruction Cycle for an SPI Transaction
Clock in the 16-bit address word
Clock in or out 16-bit data word(s)
Hold SPI_CSB high for two SPI_CLK cycles
Take SPI_CSB low and clock in the 8 bit command
Take SPI_CSB high
Production Information
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Device Terminal Descriptions
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