bc41b143a07 ETC-unknow, bc41b143a07 Datasheet - Page 39

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bc41b143a07

Manufacturer Part Number
bc41b143a07
Description
Single Chip Bluetooth
Manufacturer
ETC-unknow
Datasheet

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7
7.1
The receiver features a near-zero Intermediate Frequency (IF) architecture that allows the channel filters to be
integrated onto the die. Sufficient out-of-band blocking specification at the Low Noise Amplifier (LNA) input allows the
radio to be used in close proximity to Global System for Mobile Communications (GSM) and Wideband Code Division
Multiple Access (W-CDMA) cellular phone transmitters without being desensitised. The use of a digital Frequency Shift
Keying (FSK) discriminator means that no discriminator tank is needed and its excellent performance in the presence
of noise allows BlueCore4-ROM to exceed the Bluetooth requirements for co-channel and adjacent channel rejection.
For EDR, an ADC is used to digitise the IF received signal.
7.1.1
The LNA can be configured to operate in single-ended or differential mode. Single-ended mode is used for Class 1
Bluetooth operation; differential mode is used for Class 2 operation.
7.1.2
The Analogue to Digital Converter (ADC) is used to implement fast Automatic Gain Control (AGC). The ADC samples
the Received Signal Strength Indicator (RSSI) voltage on a slot-by-slot basis. The front-end LNA gain is changed
according to the measured RSSI value, keeping the first mixer input signal within a limited range. This improves the
dynamic range of the receiver, improving performance in interference limited environments.
7.2
7.2.1
The transmitter features a direct IQ modulator to minimise the frequency drift during a transmit timeslot, which results
in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.
7.2.2
The internal Power Amplifier (PA) has a maximum output power of +6dBm. This allows BlueCore4-ROM to be used
in Class 2 and Class 3 radios without an external RF PA.
Support for transmit power control allows a simple implementation for Class 1 with an external RF PA.
7.2.3
An 8-bit voltage Auxiliary DAC is provided for power control of an external PA for Class 1 operation or any other
customer specific application.
7.3
The radio synthesiser is fully integrated onto the die with no requirement for an external Voltage Controlled Oscillator
(VCO) screening can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in
sufficient time across the guaranteed temperature range to meet the Bluetooth v2.0 + EDR specification.
7.4
BlueCore4-ROM contains a 1.8V linear regulator which can be used to power the complete chip.
7.5
The reference clock for the system is generated from a TCXO or crystal input between 8MHz and 40MHz. All internal
reference clocks are generated using a phase locked loop, which is locked to the external reference frequency.
CS-101564-DSP12
Description of Functional Blocks
RF Receiver
Low Noise Amplifier
Analogue to Digital Converter
RF Transmitter
IQ Modulator
Power Amplifier
Auxiliary DAC
RF Synthesiser
Power Control and Regulation
Clock Input and Generation
Production Information
© CSR plc 2003-2007
Description of Functional Blocks
Page 39 of 97

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