PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 2

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

PIN DESCRIPTIONS
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
XIN
XOUT
REF[0:1]/FS[0,2]
CPUSTP#/Vtt_Pwrgd
AGP[0:1]
HTT[C/T]_[0:1]
WDRESET
PCI[0:4]
PCI5/HTTSEL
PCI6/MULTSEL
PCI7/FS1
PCI8//PCI_STOP#
PCIF/SEL24_48#
CPU[C/T]_0
CPU[C/T]_1
24_48MHz/MODE
Name
13,14,15,
Number
29,30,
Programmable Clock Generator for ALI 1681 P4 Chip Sets
26,27
33,34
18,19
39,40
43,44
5,6
45
46
12
20
23
2
3
9
8
7
Type
O
O
O
O
O
O
O
B
B
B
B
B
B
B
I
I
14.318Mhz crystal input to be connected to one end of the crystal
14.318Mhz crystal output
14.318Mhz Reference clock output. This pin latch FS[0,2] value at power-
up. (See Frequency Selection table). It has an internal pull down resistor.
At power-up, this pin is the input of Vtt_PWRGD After the first high to low,
this pin acts as CPU_STOP to disable all CPU clock outputs including when
Low. When Vtt_PWRGD input is high, FS (0:3), MULTSEL, HTTSEL and
MODE inputs are latched and all outputs are enabled. It has 120K ohm
internal pull up resistor.
AGP clock output (see Frequency table).
Differential pair output for Hyper Transport output clocks
Watch Dog reset signal will be generated after watchdog timer expires if
I2C Enable bit (Byte9.bit7) is set active
PCI clock output (see Frequency table).
This pin latches the HTTSEL value at power-up. After power-up, this pin
acts as PCI clock output. HTTSEL is used to select the current multiplier for
the HTT outputs.
If HTTSEL=0, IOH=8XIREF.
If HTTSEL=1, IOH=9XIREF. It has an internal pull-up resistor.
This pin latches the MULTSEL value at power-up. After power-up, this pin
acts as PCI clock output. MULTSEL is used to select the current multiplier
for the CPU outputs.
If MULTSEL=0, IOH=6XIREF.
If MULTSEL=1, IOH=7XIREF. It has an internal pull-down resistor.
Bi-directional pin. At power-up, the FS1 input value is latched. After power-
up, this pin acts as PCI7 output. It has an internal pull-down resistor.
When MODE=1 (pin23), this pin acts as PCI_STOP input to stop all PCI
clock outputs except PCIF when low. When MODE is low, this pin will acts
as PCI clock output. It has 120K ohm internal pull up resistor.
This pin latches SEL24_48 value at power up. After power-up, this pin acts
as PCIF clock output. SEL24_48=1, select 24Mhz. SEL24_48=0 select
48Mhz. It has 120K ohm internal pull up resistor.
Differential pair output for CPU Host.
Differential pair output for CPU Chip Sets.
This pin latches the MODE value at power-up. After power-up, this pin acts
as 24_48MHz clock output with default 24MHz or selection by I2C. MODE
function is to select mobile or desktop mode for pin 7. It has 120K ohm
internal pull up resistor.
Description
PLL202-108
Rev 8/20/02 Page 2