PLL202-13 PhaseLink (PLL), PLL202-13 Datasheet
PLL202-13
Related parts for PLL202-13
PLL202-13 Summary of contents
Page 1
... CPU Cycle to Cycle jitter: 250ps. PCI(0:6) PCI to PCI output skew: 500ps. VDD4 CPU to SDRAM output skew: 500ps. 48Mhz CPU to CPU output skew: 250ps. 24_48Mhz SDRAM to SDRAM output skew: 250ps. WDRESET CPU to PCI skew (CPU leads ns. PLL202-13 WDRESET VDDL1 ...
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... CPU2.5_3.3 input will program internal CPU skew circuits based on CPU voltage. If high, it selects 2.5V. If Low, it selects 3.3V (default). This pin is an open drain output. It will be Low at watchdog timer O expiration. O Buffered reference clock after input data latched during power-up. PLL202-13 Description Rev 02/15/00 Page 2 ...
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... PLL202-13 Spread PCI Spectrum Modulation 33 -0.5% 33 -0.5% 37.6 0.25% 33 -0.5% 33.4 0.25% 33 -0.5% 37.6 0.25% 33 -0.5% 33.4 0.25% 32 -0.5% 28.3 0.25% 31.6 0.25% 31.6 0.25% 37.3 0.25% 27.6 0.25% 32 -0.5% 33.4 0.25% 33.4 0.25% 32.3 0.25% 33.4 0.25% 37.5 ...
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... PLL202-13 Spread SDRAM PCI Spectrum Modulation 66.8 33.4 0.25% 95.0 31.6 0.25% 96.2 32 -0.5% 97.0 32 -0.5% 97.0 32.3 0.25% 100.0 33 -0.5% 100.2 33.4 0.25% 112.0 37.3 0.25% 120.0 30.0 0.25% 133.3 33 -0.5% 133.6 33.4 0.25% 138.0 34.5 0.25% 140.0 35.0 0.25% 145.0 36.2 0.25% 147 ...
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... FS2 ( see Frequency selection Table ) 1 FS1 ( see Frequency selection Table ) 0 FS0 ( see Frequency selection Table ) 0 Frequency selection control bit 1=Via I2C, 0=Via External jumper 0 FS3 ( see Frequency selection Table ) 1 0=Normal 1=Spread Spectrum enable 0 0=Normal 1=Tristate Mode for all outputs PLL202- R Rev 02/15/00 Page 5 ...
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... Inverted power up latched CPU2.5_3.3 value (Read-back only) 1 PCI6 ( Active/Inactive ) 1 PCI5 ( Active/Inactive ) 1 PCI4 ( Active/Inactive ) 1 PCI3 ( Active/Inactive ) 1 PCI2 ( Active/Inactive ) 1 PCI1 ( Active/Inactive ) 1 PCI0 ( Active/Inactive ) Default Description 1 SDRAM7 ( Active/Inactive ) 1 SDRAM6 ( Active/Inactive ) 1 SDRAM5 ( Active/Inactive ) 1 SDRAM4 ( Active/Inactive ) 1 SDRAM3 ( Active/Inactive ) 1 SDRAM2 ( Active/Inactive ) 1 SDRAM1 ( Active/Inactive ) 1 SDRAM0 ( Active/Inactive ) PLL202-13 Rev 02/15/00 Page 6 ...
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... WDT Fall-back Frequency selection for FS3 0 WDT Fall-back Frequency selection for FS2 0 WDT Fall-back Frequency selection for FS1 0 WDT Fall-back Frequency selection for FS0 0 Vendor ID Bit 2* 1 Vendor ID Bit 1* 1 Vendor ID Bit 0* PLL202-13 Revision ID Bit 3* Revision ID Bit 2* Revision ID Bit 1* Revision ID Bit 0* Vendor ID Bit 3* Rev 02/15/00 Page 7 ...
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... Watchdog Time Interval Bit 4 0 Watchdog Time Interval Bit 3 1 Watchdog Time Interval Bit 2 1 Watchdog Time Interval Bit 1 1 Watchdog Time Interval Bit 0 (LSB) PLL202-13 Description Description Device ID Bit 5* Device ID Bit 4* Device ID Bit 3* Device ID Bit 2* Device ID Bit 1* Device ID Bit 0* Rev 02/15/00 Page 8 ...
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... Motherboard Clock Generator for SIS540/630 with 133MHz FSB PROGRAMMING OF CPU FREQUENCY To simplify traditional loop counter setting, the PLL202-13 device incorporates SMART-BYTE ™ technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum performance. Detail of PLL202-13's dual mode frequency programming method is described below: 1 ...
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... I2C.Byte8.Bit(5:0). Once Enabled, WDT has to be disabled within a period that is shorter than the programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog reset pulse to provoke a system reset. After system restarts, the PLL202-13 will start from predefined Fall-back Frequency (the value of I2C Byte6,bits(7:3)). If system for any reason fails again at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery ...
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... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 I2C Register Loading: WD-TIMER, WD-ENABLE I2C Register Loading: SUCCESS = Target CPU SUCCESS = Fall-Back CPU System Restart @ PLL202-13 START Fall-Back, M, FSEL Wait For System Response FAIL - After specified WD-Timer Expired System Restart @ ...
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... All Inputs except XIN V IH All inputs except XIN Logic inputs with internal pull-down I IL2 resistors R 2,7,8,25, 3. Logic Inputs IN C XIN & XOUT pins INX PLL202-13 MIN. MAX 0 0 0 -65 ...
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... L SDRAM CPU to CPU SDRAM to SDRAM PCI to PCI Measured @ 1.5V, equal loads CPU to SDRAM SDRAM to SDRAM CPU to PCI CPU V =3.3V(2.5V REF0, PCI, 48Mhz, 24_48Mhz V =3. SDRAM REF1 PLL202- MIN. TYP. MAX =2. Rev 02/15/00 Page 13 UNITS ...
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... PCI(0: 1.5V REF0 OL REF1 24_48MHz Measured @ 1.25V CPU PCI Measured @ 1.5V REF,48MHz,24MHz Measured @ 1.25V CPU PCI Measured @ 1.5V REF,48MHz,24MHz Measured @ 1.25V CPU Measured @ 1.5V SDRAM Measured @ 1.5V PCI PLL202- MIN. TYP. MAX 105 80 110 155 55 75 105 105 ...
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... MIN (0.20 - 0.41) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202- PLL202-13 0.025 0.835 0.088 - 0.096 (2.250 - 2.450) 0.097 - 0.104 (2.467 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...