PLL202-11D PhaseLink (PLL), PLL202-11D Datasheet
PLL202-11D
Related parts for PLL202-11D
PLL202-11D Summary of contents
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... PCI Cycle to Cycle jitter: 250ps. 48Mhz SDRAM to SDRAM skew: 500ps. WDRESET# PCI to PCI skew: 500ps. CPU to CPU skew 250ps VDD3 CPU to PCI skew 4ns, typical 2ns SDRAM (0:11) SDRAMIN to SDRAM skew 4ns, SDRAM_F typical 3.5ns. PLL202-11 rev. D VDDL1 VDD1 VDD1 ...
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... SUPER I/O after input data latched during power-on. B Buffered reference clock output after input data latched during power-on. Buffer input pin: The signal provided to this input pin is buffered SDRAM outputs. O 2.5V Buffered reference clock. PLL202-11 rev. D Description Rev D 10/19/00 Page 2 ...
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... PLL202-11 rev. D SDRAM IOAPIC XTAL,VCO Running Running Running Running PCI 80 40.0 75 37.5 41.7 33.4 34.3 37.3 68 34.0 33.4 40.0 38.3 36.3 35.0 35.0 37.5 31.0 33.3 33.8 32.5 31.5 39.3 38.4 95 31.7 90 30.0 85 28.3 41.5 40.0 38.8 37.0 36 ...
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... FS1 ( see Frequency selection Table ) 0 FS0 ( see Frequency selection Table ) 0 Frequency selection control bit 1=Via I2C, 0=Via External jumper 0 I2C Selection ( see Frequency selection Table ) 1 0=Normal 1=Spread Spectrum enable, 0.25% Center Spread 0 0=Normal 1=Tristate Mode for all outputs PLL202-11 rev R Rev D 10/19/00 Page 4 ...
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... CPU_F (Active/Inactive) Default Description 1 Reserved 1 PCI_F ( Active/Inactive ) 1 Reserved 1 PCI4 ( Active/Inactive ) 1 PCI3 ( Active/Inactive ) 1 PCI2 ( Active/Inactive ) 1 PCI1 ( Active/Inactive ) 1 PCI0 ( Active/Inactive ) Default Description 1 Reserved X Inverted Power on latched FS0 value (Read only) 1 48MHz 1 24MHz 1 Reserved 1 SDRAM ( 8: Active/Inactive ) 1 SDRAM ( 4 Active/Inactive ) 1 SDRAM ( 0 Active/Inactive ) PLL202-11 rev. D Rev D 10/19/00 Page 5 ...
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... WDT Fall-back Frequency selection for FS3 0 WDT Fall-back Frequency selection for FS2 0 WDT Fall-back Frequency selection for FS1 0 WDT Fall-back Frequency selection for FS0 0 Vendor ID Bit 2* 1 Vendor ID Bit 1* 1 Vendor ID Bit 0* PLL202-11 rev. D Revision ID Bit 3* Revision ID Bit 2* Revision ID Bit 1* Revision ID Bit 0* Vendor ID Bit 3* Rev D 10/19/00 Page 6 ...
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... Watchdog Time Interval Bit 4 0 Watchdog Time Interval Bit 3 0 Watchdog Time Interval Bit 2 0 Watchdog Time Interval Bit 1 1 Watchdog Time Interval Bit 0 (LSB) PLL202-11 rev. D Description Description Device ID Bit 5* Device ID Bit 4* Device ID Bit 3* Device ID Bit 2* Device ID Bit 1* Device ID Bit 0* ...
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... Motherboard Clock Generator for 440BX Type with 133MHz FSB PROGRAMMING OF CPU FREQUENCY To simplify traditional loop counter setting, the PLL202-11 device incorporates SMART-BYTE ™ technology with a single byte programming via I2C to better optimize clock jitter and spread spectrum performance. Detail of PLL202-11's dual mode frequency programming method is described below: 1 ...
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... I2C.Byte8.Bit(5:0). Once Enabled, WDT has to be disabled within a period that is shorter than the programmed watchdog interval; otherwise WDT will generate a 500ms low watchdog reset pulse to provoke a system reset. After system restarts, the PLL202-11 will start from predefined Fall-back Frequency (the value of I2C Byte6,bits(7:3)). If system for any reason fails again at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery ...
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... Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 I2C Register Loading: WD-TIMER, WD-ENABLE I2C Register Loading: SUCCESS = Target CPU SUCCESS = Fall-Back CPU System Restart @ PLL202-11 rev. D START Fall-Back, M, FSEL Wait For System Response FAIL - After specified WD-Timer Expired System Restart @ ...
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... VIN = 0V; Inputs with I IL1 no pull-up resistors VIN = 0V; Inputs with I IL2 pull-up resistors R Pin 2,7,25,26,41, Pin 3. Logic Inputs IN C XIN & XOUT pins INX PLL202-11 rev. D MIN. MAX 0 0 0 -65 ...
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... CPU to CPU SDRAM to SDRAM PCI to PCI Measured @ 1.5V, equal loads CPU to SDRAM SDRAMIN to SDRAM CPU to PCI CPU_F,CPU1 V =3.3V(2.5V REF0,48MHz,24MHz, PCI_F,PCI V =3. SDRAM,SDRAM_F, REF1 IOAPIC V =3.3V(2.5V PLL202-11 rev MIN. TYP. MAX 250 250 500 250 3 1 ...
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... OH CPU_F (V = 2.5V 5%) DD IOAPIC CPU Measured @ 1.25V IOAPIC PCI Measured @ 1.5V REF,48MHz,24MHz CPU Measured @ 1.25V IOAPIC PCI Measured @ 1.5V REF,48MHz,24MHz Measured @ 1.25V CPU Measured @ 1.5V PCI PLL202-11 rev MIN. TYP. MAX 120 70 90 120 120 160 45 60 ...
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... MIN (0.203 - 0.406) 48PIN SSOP 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202- PLL202-11 rev. D 0.025 0.635 0.088 - 0.096 (2.235 - 2.438) 0.097 - 0.104 (2.464 - 2.642) TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE ...