PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 10

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

11. BYTE 10: Programming Mode Counter Register (1=Enable, 0=Disable)
12. BYTE 11: Spread Spectrum Modulation Amplitude Programming Register:
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Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Bit
Skew Enable
WDT Status
SST Profile
AccuSkew
Accu-SST
NAME
Name
VCO-N
Enable
Enable
Enable
SST6
SST5
SST4
SST3
SST2
SST1
SST0
-
-
Programmable Clock Generator for ALI 1681 P4 Chip Sets
Default
Default
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
AccuSkew Setting for ± 5% process independent accuracy.
1=enable, 0=disable.
Initialization setting for Skew Control and Buffer drive strength registers after
Watch dog reset.
0= Byte 12~17 initialized to 0 after WD-Reset generated.
1= Byte 12~17 unchanged after WD-Reset generated.
Watch Dog Timer Status info (read only)
0= linear, 1= non-linear
Accu-SST programming Enable: 1= via I2C Byte11, 0= via ROM setting
Enable Skew programming (byte12~14). 1=enable, 0=disable
Enable VCO-N Counter programming (byte21~22)
1= programming through setting I2C byte 21~22
0= programming through Frequency ROM setting
Spread Spectrum mode selection. 1=Center Spread, 0= Down Spread
1.
2.
Center Spread: SST<6:0> = Modulation rate * N /7
Down Spread: SST<6:0> = Modulation rate * N /14
Description
Description
PLL202-108
Rev 8/20/02 Page 10