PLL130-07 PhaseLink (PLL), PLL130-07 Datasheet

no-image

PLL130-07

Manufacturer Part Number
PLL130-07
Description
Output Level Converter Buffer , 1 Out, Translator to STD Drive CMOS, < 200MHz
Manufacturer
PhaseLink (PLL)
Datasheet
FEATURES
DESCRIPTIONS
The PLL130-07 is a low cost, high performance,
high speed, buffer that reproduces any input fre-
quency from DC to 200MHz. It provides CMOS
output with 15pF output load drive capability.
Any input signal with at least 100mV swing can
be used as reference signal. This chip is ideal
for conversion from sine wave to CMOS.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991
CMOS output
Selectable Drive capability (15pF or 30pF
output load).
Single AC coupled input (min. 100mV swing).
Input range from DC to 200 MHz.
3.3V operation.
Available in 8-Pin SOIC and 3x3mm QFN.
REF_IN
High Speed Translator Buffer to CMOS (Selectable Drive)
Amplifier
Input
DRIV_SEL
REF_IN
GND
GND
VDD
GND
GND
PIN CONFIGURATION
OE
Preliminary
14
15
13
16
(TOP VIEW)
1
2
3
4
12
PLL130-07
1
CLK_OUT
11
2
PLL130-07
10
3
9
4
8
7
6
5
8
7
6
5
Rev 10/29/02 Page 1
DRIV_SEL
VDD
GND
CLK_OUT
CLK_OUT
VDD
N/C
GND

Related parts for PLL130-07

PLL130-07 Summary of contents

Page 1

... Input range from DC to 200 MHz. 3.3V operation. Available in 8-Pin SOIC and 3x3mm QFN. DESCRIPTIONS The PLL130- low cost, high performance, high speed, buffer that reproduces any input fre- quency from DC to 200MHz. It provides CMOS output with 15pF output load drive capability. ...

Page 2

... Reference input signal. The frequency of this signal will reproduced at the output (after translation to CMOS level CMOS clock output Output enable (‘1’ for enable). Internal pull-up (default is ‘1’). SYMBOL CONDITIONS REF_IN input PLL130-07 Preliminary Description MIN. MAX 0 ...

Page 3

... 12mA -4mA OHC OH At TTL level (High drive*) At TTL level (Standard drive) SYMBOL CONDITIONS 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load 0.8V ~ 2.0V with 10 pF load 0.3V ~ 3.0V with 15 pF load PLL130-07 Preliminary MIN. TYP. MAX. UNITS 2.4 0.4 V – 0 MIN. TYP. ...

Page 4

... High Speed Translator Buffer to CMOS (Selectable Drive) PACKAGE INFORMATION 8 PIN ( dimensions Narrow SOIC Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e 1.27 BSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 TSSOP Min. Max. - 1.20 0.05 0.15 0.19 0.30 0.09 0.20 2.90 3.10 4.30 4.50 6.20 6.60 0.45 0.75 A1 0.65 BSC B e PLL130-07 Preliminary Rev 10/29/02 Page 4 ...

Page 5

... President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL130- PLL130-07 Preliminary REVISION CODE (when applicable) ...

Related keywords