PLL202-108 PhaseLink (PLL), PLL202-108 Datasheet - Page 14

• Manufacturer Part Number: PLL202-108
• Description: Ali, Via, Sis, Intel 440BX Chipset FTGS , I2C Programmable: Skew / SST / Frequency / Drive
• Manufacturer: PhaseLink (PLL)

19. Byte 18: VCO Divider Control Register
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TABLE 3: VCO Divider Programming Summary:
Bit<3:0>
1111
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit
Selection
High Speed Divider
Default
CPU-Host
CPU-CS
ROM
Divider
Divider
N/A
N/A
/14
/16
/12
/10
/4
/3
/2
/7
/8
/6
/5
-
Name
Programmable Clock Generator for ALI 1681 P4 Chip Sets
1. CPU0
2. CPU1
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Bit <3>
Bit <2>
Bit <1>
Bit <0>
Default
Selection
1
1
1
1
1
1
1
1
Mid Speed Divider
Default
ROM
/7.5
N/A
N/A
/15
/14
/16
/12
/10
/4
/3
/7
/8
/6
/5
These four bits will program VCO divider for CPUT_0 and
CPUC_0 clocks (see Table 3).
These four bits will program VCO divider for CPUC_1 and
CPUT_1 clocks (see Table 3).
1. AGP[0:1]
Selection
Default
Low Speed Divider
Description
ROM
N/A
N/A
N/A
/30
/32
/24
/20
/15
/14
/16
/12
/10
/8
/6
PLL202-108
1. PCIF,PCI
2. HTT
Rev 8/20/02 Page 14