PLL202-16 PhaseLink (PLL), PLL202-16 Datasheet
PLL202-16
Related parts for PLL202-16
PLL202-16 Summary of contents
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Clock frequency generator for VIA Pentium4 chipsets. Provides 1 REF clock, 3 CPU (including one at 2.5V for the Chipset), 3 AGP, and 9 PCI clocks. One 48MHz clock, one 24_48MHz clock. Enhanced PCI Output Drive selectable by I2C. Two ...
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Name Number SEL24_48/REF 1 XIN 4 XOUT 5 FS3/48MHz 7 FS2/24_48MHz 8 FS0/PCI_F 10 FS1/PCI0 11 MULT_SEL1/PCI1 12 14,15,17, PCI(2:7) 18,19,21 PD# 22 AGP(0:2) 23,26,27 SCLK 28 SDATA 29 WDRESET# 30 PCI_STOP# 31 CPU_STOP# 32 Vtt_PWRG# 33 47745 Fremont Blvd., ...
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CPUT(0:1) 35,40 CPUC(0:1) 34,39 IREF 37 CPUT_CS 42 CPUC_CS 41 APIC(0:1) 45,46 VDD 2,6,16,24,38,48 VDD_CPU_CS 43 VDD_APIC 48 3,9,13,20, GND 25,36,44,47 MULT_SEL1 Board target trace ( 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX ...
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FS4 FS3 FS2 FS1 FS0 ...
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When Power-Down (PD#) is sampled low by two consecutive rising edges of CPUC clock, then all clock outputs must be held low on their next high to low transition (except CPUT which must be driven high with a value ...
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Note: CPU_STOP# assertion will stop all CPU outputs. Note: PCI_F left free-running after PCI_STOP# assertion. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Assertion CPU_Stop# Waveforms Assertion ...
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A6 Address Assignment 1 Slave Provides both slave write and readback functionality Receiver/Transmitter Data Transfer Rate Standard mode at 100kbits/s The serial bits will be read or sent by the clock driver in the following order Byte 0 – Bits ...
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Bit 7 41,42 Bit 6 34,35 Bit 5 39,40 Bit 4 41,42 Bit 3 - Bit 2 - Bit 1 - Bit 0 - Bit 7 21 Bit 6 19 Bit 5 18 Bit 4 17 Bit 3 15 Bit ...
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Bit 7 7 Bit 6 8 Bit 5 - Bit 4 - Bit 3 1 Bit 2 - Bit 1 10 Bit 0 1 Bit 7 - Bit 6 - Bit 5 - Bit 4 46 Bit 3 45 Bit ...
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Bit 7 - Bit 6 - Bit 5 - Bit 4 - Bit 3 - Bit 2 - Bit 1 - Bit 0 - Note: *: Default value at power-up Bit 7 - Bit 6 - Bit 5 - Bit ...
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... To simplify traditional loop counter setting, the PLL202-16 device incorporates SMART-BYTE ™ technology with a single byte programming via I2C. Detail of PLL202-16's dual mode frequency programming method is described below: 1. ROM-table Frequency Programming: The pre-defined 32 frequencies found in Frequency table can be accessed through 3 external jumpers. ...
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... WDT will generate a 500ms low watchdog reset pulse to provoke a system reset. After system restarts, the PLL202-16 will start from predefined Fall-back Frequency (the value of I2C Byte6, bits(7:3)). If system for any reason fails again at Fall-back Frequency, the internal hardware will then generate a watchdog reset to restart the system from the value of external hardware jumper setting to ensure a safe recovery ...
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Disable WD- Enable Bit END !" F Setting !" Copy Fall-Back Frequency Setting to I2C Frequency Setting END !" Disable WD- Enable Bit !" F Frequency Setting 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 ...
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PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature Junction Temperature ESD Voltage Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the ...
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Unless otherwise stated, all power supplies = 3.3V 5%, and ambient temperature range T PARAMETERS SYMBOL Output Rise time T OR Output Fall time T OF Duty Cycle D T Clock Skew T SKEW Jitter(Cycle to Cycle) J cyc-cyc Frequency ...
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... President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER PLL202- TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE X=SSOP Rev 07/10/01 Page 16 ...