ak8823 AKM Semiconductor, Inc., ak8823 Datasheet - Page 8

• Manufacturer Part Number: ak8823
• Description: Hdtv & Ntsc/pal Multi-format Encoder Sdtv/hdtv X2 Oversampling 5ch Dacs
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
2. Pin Functional Description
MS0549-E-02
Pin name
ITU7
ITU6
ITU5
ITU4
ITU3
ITU2
ITU1
ITU0
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
CBCR7
CBCR6
CBCR5
CBCR4
CBCR3
CBCR2
CBCR1
CBCB0
CLK_SD
CLK_HD
HSYNC_SD
VSYNC_SD
HSYNC_HD
VSYNC_HD
BYPASS
IREF
FLT
HDY
HDPB
HDPR
SDY
SDC
SCL
SDA
SELA
PD_N
INIT_N
VREF_HD
VREF_SD
I/O
I/O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Pin No.
J8
K7
J7
K6
J6
J4
K3
J3
D10
D9
F9
G10
G9
H10
H9
J10
B3
A4
B4
A5
B5
B9
B10
C10
K8
A2
K2
J2
A7
B6
H2
H1
B2
D1
D2
C1
F1
F2
B7
A8
B8
C3
A3
C2
G1
Power supply
to used
IIC_VDD
IIC_VDD
IIC_VDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
AVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
Functional outline
SD Data Input pins ( ITU-R. BT.656 )
Y Data Input pins in HD Block mode
Cb / Cr Time-Division ( multiplexed ) Data Input pins
Clock Input pin for SD Block. 27MHz
Clock Input pin for HD Block. 27MHz / 74.25( 74.125 )MHz
HSYNC Timing Input pin for SD Block in Slave Mode operation.
Connect to IVSS when not in use
VSYNC Timing Input pin for SD Block in Slave Mode operation.
Connect to IVSS when not in use
HSYNC Timing Input pin for HD Block in Slave Mode operation.
Connect to IVSS when not in use
VSYNC Timing Input pin for HD Block in Slave Mode operation.
Connect to IVSS when not in use
Output pin to output On-Chip VREF voltage.
Should be connected to Analog ground via a larger-than 0.1 uF
capacitor.
Reference Current Output pin for DACs
Should be connected to AVSS via a 3.9kohm ( +/-1% ) resistor.
Filter pin for PLL
DAC Output pin for Y signal in HD block
DAC Output pin for Pb signal in HD block
DAC Output pin for Pr signal in HD block
DAC Output pin for S-pin Luminance signal in SD block
DAC Output pin for S-pin Chroma signal in SD block
I2C Bus Clock pin
I2C Bus Data pin
I2C Bus Address Select pin
Low : 40H High : 42H
Power-Down Control pin. L : PDN, H : normal operation
To initialize internal Digital filter. Initialization at “ low “.
To be pulled-up to IVDD when not in use.
To be connected to AVDD via a 0.1 uF capacitor
To be connected to AVDD via a 0.1 uF capacitor
8
[AK8823]
2006/10