ak8823 AKM Semiconductor, Inc., ak8823 Datasheet - Page 17

• Manufacturer Part Number: ak8823
• Description: Hdtv & Ntsc/pal Multi-format Encoder Sdtv/hdtv X2 Oversampling 5ch Dacs
• Manufacturer: AKM Semiconductor, Inc.

ASAHI KASEI
12. Power-Down
PD_N
PLL clock generator and registers are initialized (into default value setting) at power-down.
Hi-Z input compatible pins are as follows during this power-down.
When device output pins those are connected to the AK8823 input pins become Hi-Z conditions such as a case at the power-on
etc., the AK8823 should be powered-up in power-down condition.
This pin controls to power-down all the blocks and puts the device into the minimum power mode (Refer to item 14.Power –up
Sequence).
[ Hi-Z Compatible Input pins ]
ITU7 ~ ITU0, Y7 ~ Y0, CBCR7 ~ CBCR0
HSYNC_SD, VSYNC_SD, HSYNC_HD, VSYNC_HD
INIT_N, CLK_SD, CLK_HD
SCL, SELA
In order to put the device into the minimum power mode in normal operation ( PD_N “ H “ ), input clocks ( CLK_SD, CLK_HD )
should be stopped ( either “ L “ or “ H “ ) in addition to the following register settings.
Register Setting to put into minimum power mode
Address 0x05
Address 0x06
Address 0x15
13. Initialization
INIT_N
Video Process Digital Filter is initialized.
PLL Clock Generator and I2C register are not initialized by INIT_N.
Video Process Digital Filter can be also initialized by register (HD_SINIT_N, SD_SINIT_N), instead of INIT_N pin control.
Set INIT_N pin to “ H ( IVDD ) “ when it is not used.
PLL can be also reset by register PLL_SPD_N.
[ Initialization Registers ]
HD_SINIT_N
PLL_SPD_N
SD_SINIT_N
MS0549-E-02
L: Power-Down
“ L ”
Address 0x06 bit 2
Address 0x15 bit 4
Address 0x05 bit 7
bit 2 ~ 0 [ 000 ]
bit 2 [ 0 ], bit 1 ~ 0 [ 11 ]
bit 1 ~ 0 [ 00 ]
initialization
H : normal operation
17
2006/10
[AK8823]