ak8823 AKM Semiconductor, Inc., ak8823 Datasheet - Page 71

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ak8823

Manufacturer Part Number
ak8823
Description
Hdtv & Ntsc/pal Multi-format Encoder Sdtv/hdtv X2 Oversampling 5ch Dacs
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ASAHI KASEI
Register to adjust YC Delay amount of output signals
Sub Address 0x13 < SD Block >
Video Process 3 Register Definition
MS0549-E-02
Video Process 3 Register (R/W) [Address 0x13]
CLPLVL_SD
bit 0
bit 2
bit 3
bit 5
bit 6
bit 7
BIT
~
~
~
bit 7
1
0
Register Name
CLPLVL_SD0
CLPLVL_SD1
Reserved
SYD0
SYD2
~
~
CLPLVL_SD
bit 6
0
0
Reserved bit
S-video Y Delay bit
Clip Level bit
SYD2
bit 5
0
SYD1
bit 4
R/W
R/W
R/W
R/W
0
Default Value
71
Definition
do not write other than “0 “ s.
SDY and SDC signals can be output in up to +/- 3 system
clock time ( 27 MHz )
[ SYD2 : SYD0 ] – bit
101 : SDY component output advances 3 clock time to SDC
component.
110 : SDY component output advances 2 clock time to SDC
component.
111 : SDY component output advances 1 clock time to SDC
component.
000 : no delay between SDY component and SDC component
001 : SDY component output is delayed by 1 clock time to
SDC component.
010 : SDY component output is delayed by 2 clock time to
SDC component.
011 :SDY component output is delayed by 3 clock time to SDC
component.
to clip the under-shoot of the Over-Sampling Filter Outputs to a
pre-set value.
00 : no clipping
01 : to be clipped at approximately – 7.0 IRE
10 : to be clipped at approximately – 1.5 IRE
11 : reserved
SYD0
bit 3
0
Reserved
bit 2
0
Reserved
bit 1
0
default Value 0x00
Reserved
bit 0
2006/10
0
[AK8823]

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