ak8823 AKM Semiconductor, Inc., ak8823 Datasheet
ak8823
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ak8823 Summary of contents
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... ASAHI KASEI The AK8823 Simultaneous Output Video Encoder with on-chip 5 Channel 10 Bit DACs . As input data block, SMPTE-125M-1995 / ITU-R BT. 601, 656 compatible 4:2:2 formats ( 8 bit ) are accepted and block, SMPTE-274M-1998 ( 1080i ), SMPTE-296M-2001 ( 720p ) compatible 4:2:2 formats ( 8 bit are accepted. ...
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... O.S. Filter (1080i/720p SYNC 74.25 -> 148.5MHz Insertion (525i/625i 27MHz -> 54MHz (4:4:4) PLL (x2) (Note1) 74.25MHz -> 148.5MHz 27MHz -> 54MHz HD Block TEST2 AVDD AVSS DVDD DVSS 2 [AK8823] 27M 10 Y SDY DAC2 C SDC DAC3 BYPASS VREF_SD VREF_HD IREF FLT 54M/148.5MHz 10 HDY DAC4 HDPB DAC5 HDPR DAC6 ...
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... WSS Function ( SD ) ......................................................................................................................................49 16-5. Slave Mode ( SD ) ..........................................................................................................................................50 16-6. On-chip Color Bar ( SD ) ................................................................................................................................52 16-7. Black Burst Signal Generator Function ( SD ) ...............................................................................................52 16-8. SYNC Signal Waveform . Burst Waveform ( SD ) .........................................................................................53 17. Device Control Interface .......................................................................................................................................58 18. Register Map.........................................................................................................................................................59 19. System Connection Example................................................................................................................................78 20. Package Outline Dimensions................................................................................................................................79 21. Package Marking ..................................................................................................................................................79 MS0549-E- ).....................................................................................................................12 3 [AK8823] 2006/10 ...
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... LSB note 1 ) HDY output = 150 ohms, V all other outputs= 300 ohms Gray Scale dB note note ppm/°C mA note note 4 ) PD_N : at “ L “ setting uA note 5 ) Min. Typ. Max. 0.77IVDD 0.21IVDD +/-10 0.77IIC_VDD 0.21IIC_VDD 0.4 [AK8823] Units 2006/10 ...
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... CLK_SD / CLK_HD t 27 MHz operation CLK_SD CLK_HD Item CLK_SD CLK_HD CLK_SD / CLK_HD pulse width H CLK_SD / CLK_HD pulse width L ( note ) if this frequency shifts, color is not retrieved in SD mode in a display monitor. The AK8823 operation is not affected, though. MS0549-E-02 fCLK_HD tCLKH_HD tCLKL_HD Symbol Min. Typ. fCLK_HD 74 ...
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... VSYNC_HD, HSYNC_HD are pre-settable by register [ Address 0x05 bit 6 HVINV ]. Parameter Data Set-up Time Data Hold Time MS0549-E-02 tDH tDS Symbol Min. Typ. tDS_HD 4.4 tDH_HD 1.45 tDH tDS Symbol Min. Typ. tDS_SD 5.0 tDS_HD tDH_SD 5.0 tDH_HD 6 [AK8823] VIH VIL Max. Unit nsec nsec VIH VIL Max. Unit nsec nsec 2006/10 ...
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... Clock Pulse High Time note 1 : when to use in I2C Bus Standard mode, tSU : DAT > = 250nsec must be satisfied. note 2 : when the AK8823 is used on the not-extended tLOW Bus ( used at tLOW = minimum specification ), this condition must be satisfied. No external clock is required to write into / read from registers via I2C interface. ...
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... Low : 40H High : 42H IVDD Power-Down Control pin PDN normal operation To initialize internal Digital filter. Initialization at “ low “. IVDD To be pulled-up to IVDD when not in use. AVDD To be connected to AVDD via a 0.1 uF capacitor AVDD To be connected to AVDD via a 0.1 uF capacitor 8 [AK8823] 2006/10 ...
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... Ground pin for part Digital Power Supply pins Digital Ground pins Analog Power Supply pin Analog Ground pins left open left open Test pin Should be connected to IVSS. This pin has on-chip pull-down resistor ( 100kohm typ.). NC pins. left open. 9 [AK8823] 2006/10 ...
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... IREF VREF_SD SDY AVDD CBCR0 CBCR1 Y6 NC CBCR2 SELA SCL VSYNC_HD CBCR3 CBCR5 PD_N CBCR7 HDPB FLT VREF_HD HDY HDPR TEST2 [AK8823 IIC_VDD SDA HSYNC_HD TEST CBCR4 CBCR6 INIT_N CLK_HD NC 2006/10 ...
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... Filter Selection. Above is the normal filter for Luminance signal pass, another two types filters, Mild and soft could be selected. MS0549-E-02 Freq. - gain 6.000 Freq. - gain 2.000 4.000 11 [AK8823] 12.000 6.000 2006/10 ...
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... ASAHI KASEI 5. CbCr ( 4:2:2 4:4:4 ) Filter A 6.75 MHz rate CbCr Data is rated up to 13.5 MHz -10 -20 -30 -40 -50 -60 -70 0.000 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 0.000 MS0549-E- Freq. - gain C - 422 to 444 2.000 4.000 Freq. - gain C - 422 to 444 2.000 4.000 12 [AK8823] 6.000 6.000 2006/10 ...
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... ASAHI KASEI Filter ( 13.5 MHz rate CbCr signal is balance-modulated by the Color Sub-Carrier and the C signal is generated -10 -20 -30 -40 -50 -60 0.000 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 0.000 MS0549-E-02 Freq. - gain 4.000 8.000 Freq. - gain 4.000 8.000 13 [AK8823] 12.000 12.000 2006/10 ...
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... ASAHI KASEI 7. Video Input / Output Outline The AK8823 equips 8Bit SD Input Port ( SD Port ) at SD Block, and 16Bit HD Input Port ( HD Port ) at HD Block. Signal Capture Synchronization is selectable from 2 modes by register setting – one is to decode EAV code which is encoded on Input signal, or the other is to synchronize with HSYNC_SD / VSYNC_SD or HSYNC_HD / VSYNC_HD signals. ...
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... RFRSH MODE1,0 VRATIO VM BLKCNT [0:0] 1 [0:0] 0 [0:0] [0:0] 1 [0:0]or[0:1] 0 [0:0] 0 [0:1] [0:0] 0 [1:0] [0:0] 0 [1:1] [0:0] 0 [0:1] 1 [0:1] 0 [0:0] [0: [0:1] 0 [0:1] [0:1] 0 [1:0] [0:1] 0 [1:1] [0:1] 0 [0:0]or[0: [1:0] * [0:0] 0 [0:0] [0:0] 0 [1:1] 1 [0:1] [0:0] 0 [1:0] [0:0] 0 [1:1] [0:0] 0 [0:1] 0 [0:0] [0: [0:1] [0:1] 0 [1:0] [0:1] 0 [1:1] [0:1] 0 [1: [1:0] * AK8823 0x05 bit[5] VRPT not care bit 2006/09 ...
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... VBID processing [MHz] MODE1,0 Refresh rate 60Hz [0:0] VBID/ :1] [1:0] [1:1] * Power Down Refresh rate 50Hz [0:0] [0 :1] VBID/CC/WSS 27 [1:0] [1:1] * Power Down 16 I2C register settings 0x00 bit[0] 0x06 bit[1;0] 0x11 bit[3:2] 0x14 bit[7] RFRSH BLKCNT VM3:2 VPRTSD 1 [0:0] 0 [0:0]or[0: [1: [11 [0: [1:1] 1 [1: [11 AK8823 2006/09 ...
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... PLL clock generator and registers are initialized (into default value setting) at power-down. Hi-Z input compatible pins are as follows during this power-down. When device output pins those are connected to the AK8823 input pins become Hi-Z conditions such as a case at the power-on etc., the AK8823 should be powered-up in power-down condition. ...
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... Initialization at “ L “ and normal operating condition at “ H “. Instead of controlling this pin, same initialization function is executed by manipulating registers SD_SRST_N, HD_SRST_N. When to manipulate registers, set INIT_N pin to “ H “. POWER UP more than10msec PD_N CLK_SD/CLK_HD *PLL_SPD_N INIT_N *SD_SRST_N *HD_SRST_N *DAC on/off MS0549-E-02 DVDD / AVDD / IVDD 2msec Clock On <1> <2> <3> 18 [AK8823] 2006/10 ...
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... Register setting via I2C interface ( all other register change ) Access to the AK8823 registers is possible even when CLK_SD or CLK_HD clocks are not fed. The AK8823 register manipulation can be made anytime, but care must be taken when the power when the internal PLL oscillating frequency is changed or when the input clock is changed. ...
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... Mode Register ] ( Sub Address 0x00 ) Slave SYNC mode The AK8823 can also synchronize with externally-fed HSYNC signal and VSYNC signal as Slave SYNC mode operation. HSYNC becomes Pixel Counter Reference Point within a Line and VSYNC becomes Line Counter Reference Point within a Frame ...
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... Serration Pulse Recommended Value tolerance 16.6833 33.3667 1.5 +/- 0.1 19* lines + 1.5 0 usec +/- 0.1 3 2.3 +/- 0.1 3 4.7 +/- 0.1 3 2.3 +/- 0.1 140 +/- 20 [AK8823 300mV units msec msec usec lines usec lines usec lines usec lines usec nsec 2006/10 ...
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... measurement value point 63.556 140 140 1.5 4.7 9 lta Recommended units tolerance usec +/- 20 nsec +/- 20 nsec +/- 0.1 usec +/- 0.1 usec + 0 0.1 usec [AK8823] 2006/10 ...
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... Equalizing Pulse and Serration Pulse Measurement point 50% 50% 50 Cr0 Serration Pulse Recommended Value tolerance 2.35 +/- 0.1 4.7 +/- 0.2 2.35 +/- 0.1 200 MAX300 [AK8823] 300mV units usec usec usec nsec 2006/10 ...
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... MS0549-E- measurement value point 64.0 0.3 0.2 1.5 4.7 10 lta Recommended units tolerance usec +/- 0.1 usec +/- 0.1 usec +/- 0.3 usec +/- 0.2 usec usec [AK8823] 2006/10 ...
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... Frame Configuration : 6H 858 63 795 525 1 2 MS0549-E-02 525p ( 480p ) / 0x00 0xYY ··· ··· ··· ··· HD Vertical SYNC Signal Waveform Timing 858 795 [AK8823 2006/10 ...
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... measurement value point 31.776 70 70 0.59 2.33 4. lta Recommended units tolerance usec +/- 10 nsec +/- 10 nsec +/- 0.05 usec +/- 0.05 usec + 0 0.05 usec [AK8823] 2006/10 ...
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... For H and a, see Table 1 (ITU-R BT.1358) MS0549-E-02 HD 0x00 0xYY ··· ··· ··· ··· HD Vertical SYNC Signal Waveform Timing β Characteristics χ δ 625/50/1:1 20 49H+α* 0.15±0.05 5H* 39H* 5H* 29.65±0.1 2.35±0.1 0.1±0.05 [AK8823] 2006/10 ...
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... Build-up time (10 to 90%) of the edges of the horizontal blanking e pulse (us) Build-up time (10 to 90%) of the edges of the horizontal f synchronizing pulses (us) MS0549-E- Characteristics 28 [AK8823 lta 625/50/1:1 32 6.0±1.5 5.25 0.75±0.15 2.35±0.1 0.15±0.05 0.1±0.05 2006/10 ...
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... HD Vertical SYNC Timing 22H First Field 23H 20. 564 565 566 567 Second Field 20H 8.... 8.... 568 569 570... 583 [AK8823 584 2006/10 ...
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... Tolerance Tolerance CLK +/- 3 +/- 0.040 [usec] +0.080 [usec] +/- 3 +/- 0.040 [usec +0.080 [usec] +/- 1.5 +/- 0.020 [usec] +/- 0.002 [usec] +/- 6mV +/- 6mV - [AK8823 lta 2006/10 ...
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... HD Vertical SYNC Timing 22H 20H First Field 23H 20. 564 565 566 567 Second Field 8.... 8.... 20 568 569 570... 583 [AK8823] 21 584 2006/10 ...
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... Tolerance Tolerance CLK +/- 3 +/- 0.040 [usec] +0.080 [usec] +/- 3 +/- 0.040 [usec +0.080 [usec] +/- 1.5 +/- 0.020 [usec] +/- 0.002 [usec] +/- 6mV +/- 6mV -12 [AK8823 lta 2006/10 ...
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... EAV ( 7-2 ) Analog Output : 720p / 7-2-1 ) Frame Configuration : 745 746... 750 1 MS0549-E-02 HD 0x00 0xYY ··· ··· ··· ··· HD Vertical SYNC Timing 30H 25H 8.... [AK8823] 26 2006/10 ...
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... lta ATA Tolerance Tolerance CLK [usec] [usec] [usec] [usec] [usec] [usec] +/- 6mV +/- 6mV [AK8823 2006/10 ...
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... Analog Output : 720p / 8-2-1 ) Frame Configuration : 745 746... 750 1 MS0549-E-02 HD 0x00 0xYY ··· ··· ··· ··· EAV HD Vertical SYNC Timing 30H 25H 8.... [AK8823] 26 2006/10 ...
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... lta ATA Tolerance Tolerance CLK [usec] [usec] [usec] [usec] [usec] [usec [AK8823 2006/10 ...
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... But, in Progressive Output Modes 525p ( 480p ) / 720p, F-bit is always set to “ zero “ other than Field Blanking ( V - Blanking ) Field Blanking ( V - Blanking ) SAV EAV P3, P2, P1 Protection bits. Those bits are ignored in the AK8823. In 525i ( 480i ) / 625i ( 576i ) input cases Y port data Cr359 Y719 ...
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... ASAHI KASEI ( 2 ) EAV / SAV Codes and Line Synchronization ( HD ) The AK8823 makes Vertical Synchronization ( Line Synchronization ) with either F-bit or V-bit of EAV. In the Interlaced input signal case synchronized with F-bit. In the Progressive input signal case synchronized with V-bit. F-bit of EAV / SAV and Line relation is as follows. ...
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... F-bit MS0549-E-02 625 312 313 314 315 Line Synchronization with EAV in 625i ( 576i ) Input Mode 563 564 565 Line Synchronization ( with EAV in 1125i ( 1080i ) Input Mode 39 [AK8823 316 317 318 319 566 567 568 2006/10 ...
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... Line Synchronization with EAV in 525p ( 480p ) Input Mode 622 625 Line Synchronization with EAV in 625p ( 576p ) Input Mode 749 750 1 2 Line Synchronization with EAV in 750p ( 720p ) Input Mode ... ... [AK8823 2006/10 ...
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... Setting Functions of V-Blank Interval and Output Mode ( HD ) The AK8823 has functions to set V-Blank Interval and to control Output Mode during the V-Blank Interval. V-Blank Interval is set by [ Address : 0x01 VL1 : VL0 ] – bits of [ VBI Length & Data Delay ] register ( see the following table below ) ...
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... Adjustable Timing Function Between SYNC Signal and HDY Signal, and Between HDPB Signal and HDPR Signal ( HD ) SYNC Timing and HDY signal output relation is adjustable in the AK8823. Setting of adjustable amount is made by [ HDYPBPR Delay Register ]. Adjustable range between SYNC signal and HDY signal clocks. ...
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... HDY 3clk 3clk SYNC Signal and HDY Signal relation 15-5. Set-Up Process Function ( the AK8823, a 7.5 % set-up can be added by [ Mode Register ] setting. Set-Up process is done in the following manner. Luminance Signal = 700 [ 7 Luminance signal without set- 0.925 Chroma Signal = ( Cb/Cr signals without set- 0.925 15-6 ...
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... ASAHI KASEI 15-9. Video ID(HD) The AK8823 has a function to super-impose a Copy Protect Information CGMS-A type-A on output signal. 700mV 70 -300mV a 525i* 11.2 +/- 0.3usec (480i) ( time from 0H ) 525P* 6T (5.8 +/- 0.15usec) (480P) ( time from 1080i ( 4.15 +/- 0.16usec) 4T 720P (3.13 +/- 0.09usec) * SYNC signal waveform of 525i / p ( 480i / p ) signals differ from the above, but timing is defined based on 0H point as starting point ...
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... ASAHI KASEI 15-10. Closed Caption(HD) The AK8823 has encoding functions of the Closed Captioning and Extended Data OFF control of these functions and its data are in accordance with { Video Process 2 Register ( 12H ) } setting for SD side. As for the HD side, HD side Output can be disabled by setting Bit 3, CC_DIS at Address 0x01. ...
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... ASAHI KASEI 15-11. WSS Function ( HD D1/50Hz ) The AK8823 supports to encode WSS ( ITU-R BT.1119 ), IEC62375 which distinguish the Aspect Ratio etc.. Turning “ OFF “ of this function is controlled by HDWSS bit of { Video Process HD Register ( 07H bit [ 7 ] )}, and setting data is set at { WSS Data Register ( 0x08, 0x09 )}. ...
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... Pre-settable Frequency Resolution SCH Phase Resolution 16-2. Closed Caption(SD) The AK8823 has encoding functions of the Closed Captioning and Extended Data OFF control of these functions is in accordance with { Video Process 2 Register ( 12H ) } setting. Each Data occupies a consecutive 2 Byte Register area { Closed Caption R ( 26H, 27H )}. ...
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... ASAHI KASEI 16-3. Video The AK8823 supports to encode the Video ID ( EIAJ CPR-1204 ) which distinguishes the Aspect Ratio etc.. This is also used as CGMS ( Copy Generation Management System ). Turning “ OFF “ of this function is controlled by VBID bit of { Video Process 2 Register ( 12H )} and setting data is set at { Video ID Data Register ( 2AH, 2BH )} ...
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... ASAHI KASEI 16-4. WSS Function ( SD ) The AK8823 supports to encode the WSS ( ITU-R BT.1119 ) which distinguishes the Aspect Ratio etc.. Turning “ OFF “ of this function is controlled by WSS bit of { Video Process 2 Register ( 12H )}, and setting data is set at { WSS Data Register ( 0x18, 0x19 )}. ...
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... ASAHI KASEI 16-5. Slave Mode ( SD ) HSYNC and FID or VSYNC ( selectable by register setting ) timing signals are input when the AK8823 is in Slave mode operation. In Slave mode, the AK8823 checks transition change of HSYNC at the rise timing of SYSCLK ( refer to AC Characteristics ). Rise timing of SYSCLK right after HSYNC changes to low, is recognized to be the 32 ...
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... Digital Line-No. HSYNC VSYNC 310 311 312 Digital Line-No. HSYNC VSYNC MS0549-E- 265 266 267 268 269 625 313 314 315 316 270 271 272 273 317 318 319 320 2006/10 [AK8823] 11 274 8 ...
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... ASAHI KASEI 16-6. On-chip Color Bar ( SD ) The AK8823 can output Color Bar Signal. Color Bar Signal to be generated has 100 % Amplitude and 100% Saturation Levels. Color Bar Signal is output by setting CBG-bit of [ Video Process 1 Register ] to “ 1 “. In this case, Set-up process is performed when Set-up bit is “ ON “ and no set-up process is done when Set-up bit is “ OFF “. ...
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... measurement value point 63.556 40 140 140 300 1.5 4 cycles Recommended units tolerance usec +/- 1 IRE +/- 20 nsec +/- 20 nsec +200 -100 nsec +/- 0.1 usec +/- 0.1 usec defined by SC/H cycles + 0.2 - 0.1 usec +/- 1 cycles +/- 1 IRE [AK8823] 2006/10 ...
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... Reference 13.5MHz Clock Serration Pulse Recommended Value tolerance 16.6833 33.3667 1.5 +/- 0.1 19* lines + 1.5 0 usec +/- 0.1 3 2.3 +/- 0.1 3 4.7 +/- 0.1 3 2.3 +/- 0.1 140 +/- 20 [AK8823 286mV units msec msec usec lines usec lines usec lines usec lines usec nsec 2006/10 ...
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... 267 268 269 270 271 272 267 268 269 270 271 272 [AK8823 2006/10 ...
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... measurement value point 64.0 300 0.3 0.2 1.5 4.7 19 10.5 10 300 Recommended units tolerance usec mV +/- 0.1 usec +/- 0.1 usec nsec +/- 0.3 usec +/- 0.2 usec defined by SC/H cycles usec +/- 1 cycles mV [AK8823] 2006/10 ...
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... B : Phase of Burst : nominal Value - 135° MS0549-E-02 312 313 314 315 316 624 625 312 313 314 315 316 624 625 317 318 319 320 321 317 318 319 320 321 [AK8823] 322 322 2006/10 ...
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... SLAVE Address is depicted in 8-bits, LSB is reserved for W/R bit. [ I2C Control Sequence ] ( 1 ) Write Sequence When the Slave Address of the AK8823 Write mode is received at the first byte, Sub-Address at the second byte and Data at the third & succeeding bytes are received. There are 2 operations in Write sequence— ...
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... Closed Caption Data Write register 0x00 R/W Extended Data Write register 0x00 R/W Extended Data Write register 0x00 R/W Video ID Data Write register 0x00 R/W Video ID Data Write register 0x5A R/W write 0x00 ( note ) R/W Reserved - R Status Register 0x23 R Device ID Register Device Revision Register 0x00 R 59 [AK8823] Function Function 2006/10 ...
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... R 525p/625p 10 : 1080i 11 : 720p to appoint relation when to synchronize with HSYNC / VSYNC 0 : Data capture is done by the AK8823 timing. R done by the compatible timing specified in CEA 861B. When EAVDEC is “ 1 “, set CEA861B to “ 0 “. to select the AK8823 Sync mode R synchronized with HSYNC / VSYNC signals synchronized with EAV to set on / off of 7 ...
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... Component outputs even if data encoding is set at SD side. R/W write “ 0 “ The under-shoot part of the Over-Sampling Filter Output is clipped to a pre-set value clipping R clipped at approximately – 7.0 IRE clipped at approximately – 1.5 IRE 11 : reserved 61 [AK8823] Default Value 0x04 bit 2 bit 1 bit 0 VUNMASK VL1 VL0 ...
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... CLK time is delayed. 011 : 3 CLK time is delayed. 111 : 1 CLK time is advanced to output. 110 : 2 CLK time is advanced to output. 101 : 3 CLK time is advanced to output. 100 : reserved R/W write “ 0 “. 62 Default Value 0x00 bit 2 bit 1 bit 0 HDYDELAY HDYDEALY HDYDELAY Definition 480i/p modes, 2006/10 [AK8823 ...
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... MODE1 : MODE0 ]-bits CGMS-A function is “ OFF “ CGMS-A signal is super-imposed. R/W CGMS-A Data is set which is super-imposed on Y output of HD signal. R/W Data to be set are CGMS7 ~ CGMS14. CGMS1 ~ CGMS6 should be set at CGMS Data 1 Register. 63 [AK8823] Default Value 0x00 bit 2 bit 1 bit 0 CGMS4 CGMS5 CGMS6 0 0 ...
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... HD Port Port Polarity SYNC input signals is selected. This operates on HD Block only. R active low 1 : active hi to set Soft initialization of Filter in HD Block R initialize 1 : release 64 [AK8823] Default Value 0x00 bit 2 bit 1 bit 0 HDPR HDPB HDY Definition 2006/10 ...
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... ASAHI KASEI Powerdown Mode Control Register(R/W) [Address 0x06] Register to sets Power-Down and Operation modes of the AK8823. Sub Address 0x06 < SD Block / HD Block > bit 7 bit 6 Reserved Reserved Reserved 0 0 Power Down Mode Control Register BIT Register Name Bit0 － BLKCNT1,0 SD/HD BLOCK CNT ...
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... HDPBPR Video Signal Band Limit Filter [ HDPBPFLT 1 : HDPBPFLT Normal R Mild 10 : Soft 11 : inhibited to encode WSS signal It is turned on only when output. R WSS off 1 : WSS on 66 [AK8823] default Value 0x00 bit 2 bit 1 bit 0 HDDFMT Reserved VRATIO 2006/10 ...
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... WSS Data is written in order of 0x08 and then 0x09. When the second byte ( 0x09 ) of WSS Data is written, the AK8823 interprets that Data has been up-dated and it encodes the WSS signal on the next Video Line ( Line 23 ). Data is retained till it is up-dated with a new one ...
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... ASAHI KASEI Interface Mode Register (R/W) [Address 0x10] Register to set the AK8823 modes Sub Address 0x10 < SD Block > bit 7 bit 6 SDBLN4 SDBLN3 SDBLN2 1 0 Interface Mode Register Definition Register BIT Name bit 0 REC656 REC656 I/F mode bit bit 1 ~ Reserved Reserved bit bit 2 bit 3 ...
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... When SDBBG bit is set, SDBBG is prioritized. to output Black Burst signal 0 : input data is encoded. R Black Burst signal is output. Even when SDCBG bit is set, SDBBG is prioritized.。 0000 1111 0101 0111 0011 69 [AK8823] Default Value 0x30 bit 2 bit 1 bit 0 VM2 VM1 VM0 2006/10 ...
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... Y output at SD Block R/W When to encode Block, set “ 1 “ Extended Data off 1 : Extended data on to control encoding of WSS signal R WSS off 1 : WSS on R/W do not write other than “ 0 “s. 70 [AK8823] default Value 0x00 bit 2 bit 1 bit 0 CC284 CC21 VBID 2006/10 ...
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... SDC component. to clip the under-shoot of the Over-Sampling Filter Outputs to a pre-set value clipping R clipped at approximately – 7.0 IRE clipped at approximately – 1.5 IRE 11 : reserved 71 [AK8823] default Value 0x00 bit 2 bit 1 bit 0 Reserved Reserved Reserved 0 0 ...
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... SDYFLT 1 : SDYFLT Normal R Mild 10 : Soft 11 : inhibited R/W do not write other than “ 0 “s to set Digital Video signal which is fed to SD Block clock operation is also linked. R Port Port 72 [AK8823] default Value 0x00 bit 2 bit 1 bit 0 Reserved Reserved Reserved Definition 2006/10 ...
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... ON / OFF of SDY R Off control ON / OFF of SDC R Off R/W do not write other than “ 0 “s. to set Soft initialization of Filter in SD Block 0 : initialization R release of initialization R/W do not write other than “ 0 “s. 73 [AK8823] default Value 0x00 bit 2 bit 1 bit 0 Reserved SDC SDY 2006/10 ...
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... WSS Data is written in order of 0x18 and then 0x19. When the second byte ( 0x19 ) of WSS Data is written, the AK8823 interprets that Data has been up-dated and it encodes the Data on the next Video Line ( Line 23 ). Data is retained till it is up-dated with a new one. ...
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... Closed Caption Data is written in order of 0x26 and then 0x27. When the second byte ( 0x27 ) of Closed Caption Data is written, the AK8823 interprets that Data has been up-dated and it encodes the Data on the next Video Line. Null Codes are automatically output on those, not-data-updated lines. ...
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... VBID1 ---- VBID14 correspond to bit 1 ---- bit 14 which are described at { VBID Data Code Assignment } diagram at item { 16-3. Video Bit CRC Code from bit 15 ~ bit 20 is automatically added by the AK8823. Data is retained till it is up-dated with a new one. Status Register (R) [Address 0x34] Register to show Status of the AK8823 Sub Address 0x34 < ...
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... ASAHI KASEI Device ID Register (R) [Address 0x35] Register to indicate the AK8823 Device ID Sub Address 0x35 bit 7 bit 6 DEV7 DEV6 DEV5 0 0 Device ID Register Definition BIT Register Name bit 0 DEV0 ~ ~ Device ID bit bit 7 DEV7 Revision ID Register (R) [Address 0x36] Register to indicate the AK8823 Revision ID ...
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... PD_N RST_N Digital IIC_VDD 1.8V 1.8V 1.8V 0.1u 0.1u 0.1u MS0549-E-02 SDY - SDC - HDY - HDPB - HDPR - VREF_SD VREF_HD AK8823 FLT BYPASS IREF DVDD AVSS IVDD DVSS IVSS AVDD 0.1u 78 [AK8823] Amp + LPF HDY : 150ohm 75ohm Others : 300ohm x 5ch AVDD 0.1uF AVDD AVDD 0.1uF 620ohm 0.1u 3.9kohm Analog 3.0V 2006/10 4.7nF ...
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... Pin Count : 65 pins ( 3 ) Product Number : 8823 ( 4 ) Control Code : XYYZ ( 4 digits ) X : Year Number ( lowest, single digit ) YY : Week Number Z : Lot Number in a same week MS0549-E- Φ0.3 ± 0.05 A Φ 0. 0.08 S 8823 XYYZ 79 [AK8823 0.5 0.5 4 ...
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... AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0549-E-02 IMPORTANT NOTICE 80 [AK8823] 2006/10 ...