ak8823 AKM Semiconductor, Inc., ak8823 Datasheet - Page 18

no-image

ak8823

Manufacturer Part Number
ak8823
Description
Hdtv & Ntsc/pal Multi-format Encoder Sdtv/hdtv X2 Oversampling 5ch Dacs
Manufacturer
AKM Semiconductor, Inc.
Datasheet
ASAHI KASEI
14. Power-up Sequence
Control of Power Supply power-up and power-down
When the power supplies become stable, release PD_N pin and wait for 10 msec.
Set mode of HD / SD Blocks, then enable PLL operation first and turn on DACs.
By releasing PD_N after the power-on, rise time variations of power supplies ( DVDD / AVDD / IVDD ) are tolerated.
Wait for longer than 10 msec after PD_N is released, then enable PLL.
When to power-down, power supplies should be turned off after PD_N is activated.
When to power-up
Following timing sequence should be made after 10 msec time from the release of power-down and after input clock becomes
stable.
A longer than 2 msec transition time is required from sequence <2> to sequence <3> below.
( note 1 )
INIT_N pin is used to initialize internal digital filter. Clock input is required.
Initialization at “ L “ and normal operating condition at “ H “.
Instead of controlling this pin, same initialization function is executed by manipulating registers SD_SRST_N, HD_SRST_N.
When to manipulate registers, set INIT_N pin to “ H “.
MS0549-E-02
<1> Mode setting
<2> initialization of internal filter ( INIT_N pin “ L “ or SD_SRST_N / HD_SRST_N : 0 ) release ( note 1 ) operation which is
described below.
<3> turn on DAC
CLK_SD/CLK_HD
*HD_SRST_N
*SD_SRST_N
*PLL_SPD_N
POWER UP
*DAC on/off
INIT_N
PD_N
start of PLL operation ( PLL_SPD_N : 1 )
more than10msec
DVDD / AVDD / IVDD
Clock On
<1> <2> <3>
18
2msec
2006/10
[AK8823]

Related parts for ak8823