kac-9638 ETC-unknow, kac-9638 Datasheet - Page 24

• Manufacturer Part Number: kac-9638
• Description: Kodak Kac-9638 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
11.6
By default the sensor’s digital video port’s synchronisation sig-
nals are configured to operate in slave mode. In slave mode the
integrated timing and control block will only start frame and row
processing upon the receipt of triggers from an external source.
Partial Frame integration is disabled in this mode.Only two syn-
chronization signals are used in slave mode as follows:
Figure 50 shows the KAC-9638’s digital video port in slave
mode connected to a digital video processor master DVP.
KAC-9638
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hsync
vsync
(frame trigger)
(row trigger)
internal row
Synchronisation Signals in Slave Mode
counter
hsync
vsync
pclk
KAC-9638
Figure 50. KAC-9638 in slave mode
(row trigger)
is the row trigger input signal.
is the frame trigger input signal.
d[9:0]
hsync
vsync
hsync
d[9:0]
mclk
pclk
pclk
Figure 51. hsync slave mode timing diagram for centred display window of 642 pixels
20 pclk clock cycles
More than
(continued)
din[9:0]
RowTrig
FrameTrig
MasterClock
DVP
Figure 52. vsync slave mode timing diagram.
Minimum Valid Vsync Pulse Width
Last Row of Current Frame
X
pclk
First Pixel In The Row
24
11.7
The row trigger input pin, hsync, is used to trigger the process-
ing of a given row. It must be activated for at least two mclk
cycles. The first pixel data will appear at d[9:0] “X
after the assertion of the row trigger, were X
Where:
The polarity of the active level of the row trigger can be pro-
grammed using the HsynPol bit of the DVBUSCONFIG1 regis-
ter. By default it is active high.
11.8
The frame trigger input pin, vsync, is used to reset the row
address counter and prepare the array for row processing. It
must have a duration of least two mclk cycles and must be acti-
vated at least 20 pclk cycles after the activation of the last
hsync of the previous frame as illustrated in Figure 52.
The polarity of the active level of the row trigger is programma-
ble. By default it is active high.
HAvrg
BlkPixelEn
Row Trigger Input Pin (hsync)
Frame Trigger Input Pin (vsync)
Number Of Pixel In The Row
X
pclk
= 147 + 100*HAvrg - 8*BlkPixelEn
is the HAvrg bit setting in the VSCAN register.
is the BlkPixelEn bit setting in the
DVBUSCONFIG2 register
First Row of Next Frame
Last Pixel In The Row
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pclk
is given by:
pclk
“periods