kac-9638 ETC-unknow, kac-9638 Datasheet - Page 22

• Manufacturer Part Number: kac-9638
• Description: Kodak Kac-9638 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
,
By default the pixel clock is a free running active high (pixel data
changes on the positive edge of the clock) with a period equal to
the internal hclk. See section 6.3 for more pclk programming
modes.
11.4
The horizontal synchronisation output pin, hsync, is used as an
indicator for row data. The hsync output pin can be pro-
grammed to operate in two modes as follows:
• Level mode should be used when the pixel clock, pclk, is
• Pulse mode should be used when the pixel clock, pclk, is
By default the first pixel data at the beginning of each row is
placed on the digital video bus as soon as hsync is activated.
Furthermore, hsync is de-activated upon the placement of the
last pixel of the current row on the digital video bus the digital
video bus. It is possible to shift the start and end edges of the
hsync signal by programming the HsyncStart parameter of the
DVBUSCONFIG0 register and the HsyncEnd parameter of the
HSYNCADJUST register.
KAC-9638
pclk
d[9:0]
www.kodak.com/go/imagers 585-722-4385
hsync
pclk
d[9:0]
programmed to operate in free running mode. In level mode
the hsync output pin will go to the specified level (high or low)
at the start of each row and remain at that level until the last
pixel of that row is read out on d[9:0] as shown in Figure 43.
The hsync level is always synchronized to the active edge of
pclk. The hsync pin is put into level mode by setting the
HsyncMode bit of the DVBUSCONFIG1 register to a logic 0.
The active level of the hsync pulse is programmed using the
HsyncPol bit of the DVBUSCONFIG1 register.
programmed to operate in data ready mode. In pulse mode
the hsync output pin will produce a pulse at the end of each
row. The width of the pulse will be a minimum of four pclk
cycles and its polarity can be programmed as shown in Figure
44. The hsync level is always synchronized to the active
edge of pclk. The hsync pin is put into pulse mode by setting
the HsyncMode bit of the DVBUSCONFIG1 register to a logic
1.The active level of the hsync pulse is programmed using
the HsyncPol bit of the DVBUSCONFIG1 register.
hsync
a) hsync programmed to be active high (default)
Horizontal Synchronisation Output Pin (hsync)
pclk
d[9:0]
hsync Row n
pclk
d[9:0]
b) hsync programmed to be active low
hsync Row n
Row n
Row n
Figure 43. hsync in Level Mode
Figure 44. hsync in Pulse Mode
a) hsync programmed to be active high
b) hsync programmed to be active low
(continued)
Row n+1
Row n+1
Row n+1
Row n+1
22
11.5
The vertical synchronisation output pin, vsync, is used as an
indicator for pixel data within a frame. The vsync output pin can
be programmed to operate in two modes as follows:
• Level mode should be used when the pixel clock, pclk, is
• Pulse mode should be used when the pixel clock, pclk, is
By default the first pixel data at the beginning of each frame is
placed on the digital video bus as soon as vsync is activated.
Furthermore, vsync is de-activated upon the placement of the
last pixel of the current frame on the digital video bus. It is possi-
ble to shift the start and end edges of the vsync signal by pro-
gramming the VsyncStart parameter of the DVBUSCONFIG0
register and the VsyncEnd parameter of the VSYNCADJUST
register.
pclk
d[9:0]
vsync
pclk
d[9:0]
programmed to operate in free running mode. In level mode
the vsync output pin will go to the specified level (high or low)
at the start of each frame and remain at that level until the last
pixel of the last row in the frame is placed on d[9:0] as shown
in Figure 45. The hsync level is always synchronized to the
active edge of pclk. The vsync pin is put into level mode by
setting the VsyncMode bit of the DVBUSCONFIG1 register to
a logic 0. The active level of the vsync is programmed using
the VsyncPol bit of the DVBUSCONFIG1 register.
programmed to operate in data ready mode. In pulse mode
the vsync output pin will produce a pulse at the end of each
frame. The width of the pulse will be a minimum of four hclk
cycles and its polarity can be programmed as shown in Figure
46. The vsync level is always synchronized to the active edge
of pclk. The vsync pin is put into pulse mode by setting the
VsyncMode bit of the DVBUSCONFIG1 register to a logic 1.
The active level of the vsync pulse is programmed using the
VsyncPol bit of the DVBUSCONFIG1 register.
vsync
invalid pixel data
invalid pixel data
Vertical Synchronisation Pin (vsync)
pclk
d[9:0]
b) vsync programmed to be active low (default)
vsync
pclk
d[9:0]
b) vsync programmed to be active low
vsync
a) vsync programmed to be active high
Frame n
Frame n
Figure 46. vsync in pulse mode
Figure 45. vsync in Level Mode
a) vsync programmed to be active high
Frame n
Frame n
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Frame n+1
Frame n+1
Frame n+1
Frame n+