kac-9637 ETC-unknow, kac-9637 Datasheet

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kac-9637

Manufacturer Part Number
kac-9637
Description
Cmos Image Sensor 648 H X 488 V Vga 68 Fps Monochrome Cis
Manufacturer
ETC-unknow
Datasheet
IMAGE SENSOR SOLUTIONS
www.kodak.com/go/imagers 585-722-4385
PERFORMANCE
SPECIFICATION
DEVICE
September 2004
Revision 1.92
CMOS IMAGE SENSOR
KODAK KAC-9637
Monochrome CIS
VGA 68 fps
648 (H) X 488 (V)
1
Email:imagers@kodak.com

Related parts for kac-9637

kac-9637 Summary of contents

Page 1

... IMAGE SENSOR SOLUTIONS DEVICE PERFORMANCE SPECIFICATION KODAK KAC-9637 CMOS IMAGE SENSOR 648 (H) X 488 (V) VGA 68 fps Monochrome CIS September 2004 Revision 1.92 www.kodak.com/go/imagers 585-722-4385 1 Email:imagers@kodak.com ...

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... IMAGE SENSOR SOLUTIONS KAC-9637 Monochrome CMOS Image Sensor VGA 68 FPS General Description The KAC-9637 is a high performance, low power, 1/4" VGA CMOS Active Pixel Sensor capable of capturing monochromes- till or motion images and converting them to a digital data stream. Great image quality is achieved by integrating a high perfor- ...

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... I C Compatible Power POR Control Serial I/F Master Sensor Controller Amp 10 bit A/D Figure 1. Chip Block Diagram KAC-9637 8 32 PIN LCC Figure 2. Chip Pin Diagram 3 mclk clk gen snapshot extsync d[9:0] pclk hsync ...

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... Scan Read Out Direction (0,0) lens Figure 4. Scan directions and position of origin in imaging system www.kodak.com/go/imagers 585-722-4385 System Control Serial Control Bus KAC-9637 Digital Video Bus Figure 3. Typical Application Diagram (0,0) digital out (0,0) horizontal scan pin 1 ...

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IMAGE SENSOR SOLUTIONS Pin Descriptions Pin Name I/O Typ Description Digital output. Bit 5 of the digital video output bus. This output can be tri-stated Digital output. Bit 6 of the digital ...

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IMAGE SENSOR SOLUTIONS Pin Descriptions (continued) Pin Name I/O Typ Description 24 pclk O D Digital output. The pixel clock. 25 mclk I D Digital input. The sensor’s master clock input. 26 vss_dig volt power supply for ...

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IMAGE SENSOR SOLUTIONS Absolute Maximum Ratings (Notes 1 & 2) Any Positive Supply Voltage Voltage On Any Input or Output Pin Input Current at any pin (Note 3) Package Input Current (Note 3 Package Dissipation 25°C A ...

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... The values for maximum power dissipation listed above will be reached only when the KAC-9637 is operated in a severe fault condition. Note 5: Human body model is 100pF capacitor discharged through a 1.5kΩ resistor. Machine model is 220pF discharged through ZERO Ohms ...

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IMAGE SENSOR SOLUTIONS CMOS Active Pixel Array Specifications Parameter Number of pixels (row, column) Total Active Array size (x,y Dimensions) Total Active Pixel Pitch Fill Factor without micro-lens Image Sensor Specifications The following specifications apply for All VDD pins = ...

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IMAGE SENSOR SOLUTIONS Sensor Response Curves 450 400 350 300 250 200 150 100 50 0 400 500 www.kodak.com/go/imagers 585-722-4385 600 700 Figure 5. Spectral Response Curve 10 (no micro lens) 800 900 Wavelength [nm] Email:imagers@kodak.com ...

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... OVERVIEW 1.1 Light Capture and Conversion The KAC-9637 contains a CMOS active pixel array consisting of 488 rows by 648 columns. 24 columns of optically shielded (black) pixels are provided to the right of the array as shown in Figure 6. Only the middle 8 black columns are used for black level compensation. The black pixels are physically located at the end of each row but are read out first ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued) 2.0 DOUBLE BUFFERED REGISTERS All programmable registers that effect the frame rate and inte- gration timing are double buffered; such that the new values only take effect at the start of the new frame. ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued) 5.0 SUB-SAMPLING MODES 5.1 2:1 Sub-Sampling The timing and control circuit can be programmed to sub-sam- ple pixels in the “Active Window” vertically, horizontally or both, with an aspect ratio of 2:1 as illustrated ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued) 5.3 4:2 Sub-Sampling The timing and control circuit can be programmed to sub-sam- ple pixels in the display window vertically, horizontally or both, with an aspect ratio of 4:2 as illustrated in figure 15 ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued) 6.0 FRAME RATE & EXPOSURE CONTROL 6.1 Introduction The frame time is defined as the time it takes to reset every pixel in the array, integrate the incident light, convert it to digital data ...

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... Clock Generation The KAC-9637 contains a clock generation module (figure 19) that will create three clocks as follows: Hclk, the horizontal clock. This is an internal system clock and can be programmed to be the input clock (mclk) or mclk divided by 2 All exposure times are in multiples of this clock. ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued) 6.4 Full Frame Integration Full frame integration is when each pixel in the array integrates light incident on it for the duration of a frame (see Figure 20). The number of pixels processed per ...

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... BLACK LEVEL & OFFSET ADJUSTMENT The KAC-9637 allows for both fine and coarse black level adjustment. Coarse adjustment is made using the PIXELOFF- SET register and only needs to be done once at power up. Fine offset adjustment is done on a row basis and can be accom- ...

Page 19

... Device Address The Device Address can be changed by writing to the I2cDevAddr parameter in the I2CMODE Register. 9.3 Acknowledgment The KAC-9637 will hold the value of the sda pin to a logic 0 dur- ing the logic 1 state of the Acknowledge clock pulse on sclk as shown in Figure 23. sda MSB from master ...

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... Processor KAC-9637 Connected bit Digital Image Processors Figure 30. Example of connection to 10/8 bit systems www.kodak.com/go/imagers 585-722-4385 Synchronisation Signals in Master Mode In master mode the integrated timing and control block controls the flow of data onto the 12-bit digital port, three synchronisation ...

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IMAGE SENSOR SOLUTIONS Functional Description (continued default the pixel clock is a free running active high (pixel data changes on the positive edge of the clock) with a period equal to the internal hclk. See section 6.3 for ...

Page 22

IMAGE SENSOR SOLUTIONS Functional Description (continued) pclk vsync hsync d[9: row1 frame 1 Programmable hsync to 1st valid pixel delay ...

Page 23

... Only two synchronization signals are used in slave mode as fol- lows: hsync is the row trigger input signal. vsync is the frame trigger input signal. Figure 41 shows the KAC-9637’s digital video port in slave mode connected to a digital video processor master DVP. d[9:0] din[9:0] hsync RowTrig ...

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IMAGE SENSOR SOLUTIONS MEMORY MAP ADDR Register 00h DEVID 01h REV 02h - 04h 05h VCLKGEN 06h PWD&RST 07h I2CMODE 08h 09h OPCTRL 0Ah - 0Fh 10h VIDCONFIG 11h VSCAN HSCAN 14h 15h ITIMECONFIG 16h-18h 19h WROWS ...

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IMAGE SENSOR SOLUTIONS MEMORY MAP (continued) ADDR Register 50h VSYNCADUST 51h HSYNCADUST 52h DVBUSCONFIG0 53h DVBUSCONFIG1 54h DVBUSCONFIG2 55h DVBUSCONFIG3 56h - 7Fh 80h INITREG1 81h - 82h 83h PIXELOFFSET 84h 85h POWCTRL 86h - 87h 88h INITREG2 www.kodak.com/go/imagers 585-722-4385 ...

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... IMAGE SENSOR SOLUTIONS Register Set The following section describes all available registers in the KAC-9637 register bank and their function. Register Name Device ID Address 00 Hex Mnemonic DEVID Type Read Only Reset Value 47 Hex Bit Bit Symbol Description 7:0 DevId The sensor’s device ID. ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Video Configuration Register Address 10 Hex Mnemonic VIDCONFIG Type Read/Write Reset Value 01 Hex. Bit Bit Symbol Description 7:1 Reserved. 0 Color Set to a logic 1, (the default), to configure the ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Active Window Row Start Register Address 19 Hex Mnemonic WROWS Type Read/Write (Double Buffered) Reset Value 00 Hex. Bit Bit Symbol Description 7:0 WStar- Use to program the display win- tRow[10:3] dow’s ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Frame Delay High Register Address 20 Hex Mnemonic FDELAYH Type Read/Write (Double Buffered) Reset Value 00 Hex. Bit Bit Symbol Description 7:0 Fdelay[14:7] Use to program the MSBs of the frame delay. ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name PGA Register Address 42 Hex Mnemonic PGA Type Read/Write Reset Value 00 Hex. Bit Bit Symbol Description 7 Reserved 6:0 PGA Use to program the analog gain. Max gain is 16dB of ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name VSYNC Latency Register Address 50 Hex Mnemonic VSYCADJUST Type Read/Write Reset Value 08 Hex. Bit Bit Symbol Description 7:6 Reserved. 4:0 VsyncEnd By default, in pulse mode the vsync signal will remain ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Polarity Adjustment Register Address 53 Hex Mnemonic DVBUSCONFIG1 Type Read/Write Reset Value 0C Hex. Bit Bit Symbol Description 7 Reserved 6 PixClkMode Set the to a logic 1 to operate pclk to ...

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IMAGE SENSOR SOLUTIONS Register Set (continued) Register Name Video Output Tristate Adjustment Register Address 55 Hex Mnemonic DVBUSCONFIG3 Type Read/Write Reset Value 00 Hex.Register Set (continued) Bit Bit Symbol Description 7:5 Reserved 4 Tristate Digital output tristate. Set this bit ...

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IMAGE SENSOR SOLUTIONS Timing Information 1.0 DIGITAL VIDEO PORT MASTER MODE TIMING LEVEL MODE pclk hsync t1 d[9:0] pclk vsync t5 hsync Rn pclk vsync t5 hsync F n delay delay delay Inter Frame Delay Figure 46. ...

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IMAGE SENSOR SOLUTIONS Timing Information 2.0 DIGITAL VIDEO PORT MASTER MODE TIMING PULSE MODE pclk hsync t2 t3 P639 d[9:0] pclk vsync hsync t6 vsync t5 t6 hsync F n-2 R479 delay Inter Frame Delay Figure 49. Frame Delay Timing ...

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IMAGE SENSOR SOLUTIONS Timing Information (continued) 3.0 DIGITAL VIDEO PORT SLAVE MODE TIMING hsync trigger row n d[9:0] P640 mclk Row n-1 Figure 50. Slave Mode Row Trigger and Readout Timing trigger last row hsync in frame n t5 trigger ...

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IMAGE SENSOR SOLUTIONS 1. See section 10.6 for definition of X mclk Timing Information (continued) mclk vsync hsync Figure 53. Set up and Hold Times for Slave Mode PARAMETER Vsync rising edge to Mclk rising (set-up time) Hsync rising edge ...

Page 38

IMAGE SENSOR SOLUTIONS Timing Information (continued) 1.0 SERIAL BUS TIMING Sr t fDA t fDA sda t HD;DAT t t SU;STA HD;STA sclk t rCL = Rp resistor pull-up = MCS current source pull-up (1) Rising edge of the first ...

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IMAGE SENSOR SOLUTIONS Mechanical Information Dimension Description A Distance from top of die to bottom of cavity B Top of die to top of glass lid C Top of package to bottom of glass lid D ...

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IMAGE SENSOR SOLUTIONS Package Information * * ...

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