kac-9638 ETC-unknow, kac-9638 Datasheet - Page 20

• Manufacturer Part Number: kac-9638
• Description: Kodak Kac-9638 Cmos Image Sensor
• Manufacturer: ETC-unknow

IMAGE SENSOR SOLUTIONS
Functional Description
10.0 SERIAL BUS
The serial bus interface consists of the sda (serial data), sclk
(serial clock) and sadr (device address select) pins. The KAC-
9638 I2C interface can operate only as a slave.
The sclk pin is an input, it only controls the serial interface, all
other clock functions within KAC-9638 use the master clock pin,
mclk. Mclk must be active and at least 4 times faster than sclk
for the serial interface to work properly.
10.1
The serial bus will recognize a logic 1 to logic 0 transition on the
sda pin while the sclk pin is at logic 1 as the start condition. A
logic 0 to logic 1 transition on the sda pin while the sclk pin is at
logic 1 is interrupted as the stop condition as shown in Figure
31.
10.2
The serial bus Device Address of the KAC-9638 is set to
1010101 when sadr is tied low and 0110011 when sadr is tied
high. The value for sadr is set at power up.
The Device Address can be changed by writing to the
I2cDevAddr parameter in the I2CMODE Register.
10.3
The KAC-9638 will hold the value of the sda pin to a logic 0 dur-
ing the logic 1 state of the Acknowledge clock pulse on sclk as
shown in Figure 32.
KAC-9638
www.kodak.com/go/imagers 585-722-4385
sda
sclk
sda
sclk
from master
sda
sclk
sda
from sensor
Start/Stop Conditions
Device Address
Acknowledgment
start condition
START
S
S
S
S
Figure 31. Start/Stop Conditions
Device
Address
Figure 32. Acknowledge
MSB
1
MSB
1
2
2
W
S
(continued)
A
7
Address
Device
7
stop condition
Figure 35. Serial Bus Write Operation
Figure 36. Serial Bus Read Operation
Register
Address
Figure 34. Serial Bus Byte Format
8
Clock pulse
P
for ACK
W
byte complete
8
9
from receiver
A
ack signal
ACK
ACK
ACK
A
9
Register
Address
20
clock line
held low
S
followed by the sensor’s Device Address and Write bit. When
dition. See Figure 36.
10.8
Several addresses can be written to without the need to re-start
by setting the AdvWr bit in the I2CMODE register to a logic 1.
10.4
The master must ensure that data is stable during the logic 1
state of the sclk pin. All transitions on the sda pin can only
occur when the logic level on the sclk pin is “0” as shown in Fig-
ure 33
10.5
Every byte consists of 8 bits. Each byte transferred on the bus
must be followed by an Acknowledge. The most significant bit of
the byte is should always be transmitted first. See Figure 34.
10.6
A write operation is initiated by the master with a Start Condition
the master receives an Acknowledge from the sensor it can
transmit an 8-bit internal register address. The sensor will
respond with a second Acknowledge signaling the master to
transmit 8 write data bits. A third Acknowledge is issued by the
sensor when the data has been successfully received.
The write operation is completed when the master asserts a
Stop Condition or a second Start Condition. See Figure 35.
10.7
A read operation is initiated by the master with a Start Condition
followed by the sensor’s Device Address and Write bit. When
the master receives an Acknowledge from the sensor it can
transmit the internal Register Address byte. The sensor will
respond with a second Acknowledge. The master must then
issue a new Start Condition followed by the sensor’s Device
Address and read bit. The sensor will respond with an Acknowl-
edged followed by the Read Data byte.
The read operation is completed when the master asserts a Not
Acknowledge followed by Stop Condition or a second Start Con-
sda
sclk
Address
A
Device
Data Valid
Byte Format
Write Operation
Read Operation
Advanced Write Mode
1
Data
Byte
data valid
data line
stable;
2
Figure 33. Data Validity
R
A
P
A
change
of data
allowed
8
Data
Byte
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ACK
bold sensor action
9
data valid
data line
from receiver
bold sensor action
stable;
ack signal
_
A
P
P