sii1160 Silicon image, sii1160 Datasheet - Page 29

• Manufacturer Part Number: sii1160
• Description: Sii 1160 Panellink Transmitter
• Manufacturer: Silicon image

SiI 1160 PanelLink Transmitter
Data Sheet
C
R
Detail of Source termination (magnified)
R and C 0603 components installed.
Figure 18. Source Termination Layout Illustration
The layout in Figure 18 has been developed to minimize trace stubs on the differential TMDS lines, while
providing pads for the source termination components (left-hand magnified view). Source termination components
should be placed close to the transmitter pins. The resistor and capacitor are shown installed on the pads
provided (right-hand magnified view).
Differential Trace Routing
The routing for the SiI 1160 chip is relatively simple since no spiral skew compensation is needed. However, a few
small precautions are required to achieve the full performance and reliability of DVI.
The Transmitter can be placed fairly far from the output connector, but care should be taken to route each
differential signal pair together and achieve impedance of 100Ω between the differential signal pair. However,
note that the longer the differential traces are between the transmitter and the output connector, the higher the
chance that external signal noise will couple onto the low-voltage signals and affect image quality.
Do not split or have asymmetric trace routing between the differential signal pair. Vias are very inductive and can
cause phase delay problems if applied unevenly within a differential pair. Vias should be minimized or avoided if
possible by placing all differential traces on the top layer of the PCB.
Figure 19 illustrates an incorrect routing of the differential signal from the SiI 1160 to the DVI connector. Figure 20
illustrates the correct method to route the differential signal from the SiI 1160 to the DVI connector. Figure 21
illustrates recommended routing for differential traces at the DVI connector.
SiI-DS-0126-B
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