sii1160 Silicon image, sii1160 Datasheet - Page 14

• Manufacturer Part Number: sii1160
• Description: Sii 1160 Panellink Transmitter
• Manufacturer: Silicon image

Reserved Pins
It is preferable to tie indicated pins HIGH through a 2-5KΩ resistor; direct connection to VCC is not
recommended.
Power and Ground Pins
SiI-DS-0126-B
Pin Name
Pin Name
PGND1
PGND2
PVCC1
PVCC2
AGND
AVCC
IVCC
GND
VCC
RSVD
RSVD
RSVD
RSVD
Pin #
22
28
29
38
7,31,57,67,79,89
17,66,81,98
33,37,41,47
8,30,56,88
36,44
Pin #
18
85
19
86
Type
In
In
In
--
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Must be tied HIGH for normal operation.
Reserved. Should be left unconnected (but can be tied to AVCC for existing
SiI 160 designs).
Ground
Ground
Ground
Ground
Power
Power
Power
Power
Power
Type
10
Digital Core VCC, must be set to 3.3V.
Digital Core GND.
Input VCC, must be set to 3.3V.
Analog VCC must be set to 3.3V.
Analog GND.
Primary PLL Analog VCC must be set to 3.3V.
Filter PLL Analog VCC must be set to 3.3V.
PLL Analog GND. PGND1 should not be directly
connected to PGND2 before being connected to the
GROUND plane. They should be connected individually
to the GROUND plane.
PLL Analog GND. PGND2 should not be directly
connected to PGND1 before being connected to the
GROUND plane. They should be connected individually
to the GROUND plane.
Description
Description
SiI 1160 PanelLink Transmitter
Data Sheet