sii1160 Silicon image, sii1160 Datasheet - Page 12

• Manufacturer Part Number: sii1160
• Description: Sii 1160 Panellink Transmitter
• Manufacturer: Silicon image

Pin Descriptions
Input Pins
Control and Configuration Pins
SiI-DS-0126-B
SS_CLK_OUT
SS_CLK_IN
Pin Name
Pin Name
SS_EN#
HSYNC
VSYNC
DIE23-
DIO23-
EDGE
RSVD
CTL1
CTL2
CTL3
DIO0
IDCK
DIE0
PIXS
DE
Diagram
Diagram
SiI 1160
SiI 1160
Pin #
Pin #
See
See
Pin
Pin
80
78
76
77
24
25
84
83
82
27
Type
Type
Out
In
In
In
In
In
In
In
In
In
In
In
In
Input Even Data[23:0] corresponds to 24-bit pixel data for 1-pixel/clock input mode and to
the first 24-bit pixel data for 2-pixels/clock mode.
Input data is synchronized with Input data clock (IDCK).
Data can be latched on the rising of the falling edge of IDCK depending on whether
EDGE is high or low, respectively.
Refer to TFT Panel Data Mapping in this document and DSTN Panel Data Mapping
application note (SiI-AN-0007-A), which tabulates the relationship between the input data
to the transmitter and output data from the Receiver
Input Odd Data[23:0] corresponds to the second 24-bit pixel data for 2-pixels/clock mode.
Tie all pins to low when not in use.
Input data is synchronized with Input data clock (IDCK).
Data can be latched on the rising of the falling edge of IDCK depending on whether
EDGE is high or low, respectively.
Dual Link is not supported.
Input Data Clock. Input data and control signals can be valid either on the falling or the
rising edge of IDCK as selected by the EDGE pin.
Input Data Enable. This signal qualifies the active data area. DE is always required by the
transmitter and must be high during active display time and low during blanking time.
Horizontal Sync input control signal.
Vertical Sync input control signal.
Data/Control Latching Edge. A LOW level indicates that all input signals(DIE/DIO[23:0],
HSYNC, VSYNC, DE and CTL[3:1] are latched on the falling edge of IDCK, while a HIGH
level(3.3V) indicates that all input signals are latched on the rising edge of IDCK. When
the I
bit is used instead.
Pixel Select. A LOW level indicates one pixel (up to 24-bits) per clock mode using
DIE[23:0]. A HIGH level (3.3V) indicates two pixels (up to 48-bits) per clock mode using
DIE[23:0] for the first pixel and DIO[23:0] for the second pixel.
General Input control signal 1.
Spread Spectrum Clock Input (future). A planned future variation of this device will allow
a spread spectrum version of SS_CLK_OUT to be driven into this pin, at which time pin
29 will become CTL1.
General Input control signal 2.
Spread Spectrum Clock Output (future). A planned future variation of this device will
allow a clock to be driven out of this pin for conditioning by a spread spectrum device, at
which time pin 28 will become CTL2.
General Input control signal 3.
Reserved. Must be tied HIGH for normal operation.
Spread Spectrum Enable. A planned future variation of this device will use this pin to
enable pins 83 and 84 to handle spread spectrum clock.
Low = Spread Spectrum feature enabled on pins 83 and 84
High = Pins 83 and 84 are CTL2 and CTL1 outputs (default)
2
C interface is enabled (ISEL/RST=LOW), this pin is ignored and the EDGE register
8
Description
Description
SiI 1160 PanelLink Transmitter
Data Sheet