sii1160 Silicon image, sii1160 Datasheet - Page 15

• Manufacturer Part Number: sii1160
• Description: Sii 1160 Panellink Transmitter
• Manufacturer: Silicon image

SiI 1160 PanelLink Transmitter
Data Sheet
Feature Information
I
The SiI 1160 Tx provides an I
is optional and is selected by the ISEL/RST pin. If not used, the chip register settings return to a default state; the
EDGE and PD features then come under the control of the respective strap pins instead.
The I
clock and input is required to read and write to the I
also take place using only the SCL clock in power down mode.
The transmitter responds to the seven-bit binary I
bit 0 of the I
read transaction.
The I
2
C Interface
2
2
C slave state machine operates from an internal clock derived from the incoming SCL signal. No video
C read operation is shown in Figure 9, and the write operation in Figure 10. Page mode is not supported.
Bus Activity :
2
Master
C address. Setting this bit to 0 will enable a write transaction and setting this bit to 1 will enable a
SDA
Bus Activity :
Master
SDA
S
Slave Address
2
C slave interface for more precise control of the chip features. Use of this interface
S
Slave Address
A
C
K
Figure 10. I
Register Address
Figure 9. I
2
C address of 0x70. A read or write transaction is determined by
2
C registers from address 0x00 to 0x0F. These accesses can
A
C
K
Register Address
2
2
11
C Byte Read
C Byte Write
A
C
K
S
Slave Address
A
C
K
Data
A
C
K
Data
A
C
K
P
No
SiI-DS-0126-B
A
C
K
P