sii1160 Silicon image, sii1160 Datasheet - Page 17

• Manufacturer Part Number: sii1160
• Description: Sii 1160 Panellink Transmitter
• Manufacturer: Silicon image

SiI 1160 PanelLink Transmitter
Data Sheet
Notes:
Dual Zone PLL
The SiI 1160 Tx offers a dual-zone PLL that changes its operational parameters depending on the frequency zone
selected. In the low zone, operation is ideal in the low frequency range, from 20MHz to around 120MHz. High
zone operation is optimized in the high frequency range, above 100MHz. In the overlapping range, either low
zone or high zone operation can be used.
Operating zone optimization contributes to robust operation over long cables. For example, optimized PLL
characteristics account for the ability of the transmitter to send video at UXGA over 20m cables.
PLL zone selection is controlled either manually or automatically. Manual zone control is the preferred mode of
operation.
Manual Zone Control
Whenever the application allows it, PLL zone selection should be made manually. The I
and EZONE allow the host graphics controller to set the optimal zone for the current video resolution being
transmitted. For frequencies over 100MHz, the controller should select high zone PLL operation. Table 2
describes the relevant register bits.
Register Name
FRQ_HIGH
FRQ_LOW
DEV_REV
VND_IDH
DEV_IDH
VND_IDL
DEV_IDL
1. RO = Read Only Registers
2. RW = Read/Write Registers
3. ‘Default’ indicates value set after a reset event. Not all bits default to a defined state after reset.
EDGE
RSEN
CTL0
HEN
VEN
PD
Access
RW
RW
RW
RW
RW
RO
RO
RO
RO
RO
RO
RO
RO
Vendor ID Low byte (0x01)
Vendor ID High byte (0x00)
Device ID Low byte (0x06)
Device ID High byte (0x00)
Device Revision (0x00)
IDCK. Low frequency limit is 25MHz. (0x19)
IDCK High frequency limit is 165MHz. Value is offset over 65MHz. (0x64)
Horizontal Sync Enable
0 – HSYNC input is transmitted as fixed LOW
1 – HSYNC input is transmitted as input. → Default
Vertical Sync Enable
0 – VSYNC input is transmitted as fixed LOW
1 – VSYNC input is transmitted as input. → Default
Edge Select (same function as EDGE pin)
0 – Input data low order bits latched first → Default
1 – Input data high order bits latched first
Power Down mode (same function as PD# pin)
0 – Power Down. → Default after RESET
1 – Normal operation
Receiver Sense. This bit is HIGH if a powered on receiver is connected to the transmitter
outputs, LOW otherwise. This function is only available for use in DC-coupled systems.
Control 0. CTL0, CTL1, CTL2, CTL3 are sent over TMDS interface when DE is LOW.
CTL1-3 are driven in from external pins, but CTL0 is not available externally and therefore
must be set through this register. Set to 0 for HDMI applications.
0 – Transmit CTL0 as LOW
1 – Transmit CTL0 as HIGH
Note that when not in I
Table 1. General I
2
C mode, CTL0 is always transmitted as HIGH.
13
2
C Register Bits
Description
2
C register bits ZONEF
SiI-DS-0126-B