k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 52

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
AC CHARACTERISTICS (I-II)
Note : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the
DQS out access time from CK
CK high-level width
CK low-level width
CK cycle time
WRITE Latency
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
Active termination setup time
Active termination hold time
DQS input high pulse width
DQS input low pulse widthl
Data strobe edge to Dout edge
DQS read preamble
DQS read postamble
Write command to first DQS latching transition
DQS write preamble
DQS write preamble setup time
DQS write postamble
Half strobe period
Data output hold time from DQS
Data-out high-impedance window
from CK and /CK
Data-out low-impedance window from
CK and /CK
Address and control input hold time
Address and control input setup time
Address and control input pulse width
Jitter over 1~6 clock cycle error
Cycle to cycle duty cycle error
Rise and fall times of CK
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be driven high by the controller. WDQS can not be pulled high by
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
5. The cycle to cycle jitter over 1~6 cycle short term jitter
input buffers are turned on during the WRITE commands for lower power operation.
ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 4 ~7 clocks which must be greater than 7ns, the
the on-die termination alone.
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
Parameter
CL=11
CL=10
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
tJ
tDCERR
tR, tF
DQSCK
CH
CL
CK
WL
DH
DS
ATS
ATH
DQSH
DQSL
DQSQ
RPRE
RPST
DQSS
WPRE
WPRES
WPST
HP
QH
HZ
LZ
IH
IS
IPW
Symbol
52 / 54
1,2,3,6,7
tCLmin or
t
HP
WL-0.2
tCHmin
-0.140
-0.23
0.45
0.45
1.25
0.16
0.16
0.48
0.48
0.35
Min
-0.3
-0.3
1.4
0.4
0.4
0.4
0.3
0.3
0.9
10
10
-0.14
0
-
-
-
-BC12
WL+0.2
+0.23
0.140
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
256M GDDR3 SDRAM
1,2,3,5,6,7
tCLmin or
t
HP
tCHmin
-0.160
WL-0.2
-0.26
0.45
0.45
0.18
0.18
0.48
0.48
0.35
0.35
Min
-0.3
-0.3
1.4
0.4
0.4
0.4
0.4
1.0
10
10
-0.16
0
-
-
-
-
-BC14
Rev. 1.3 May 2007
WL+0.2
+0.26
0.160
Max
0.55
0.55
0.52
0.52
0.03
0.03
3.3
0.6
0.6
0.6
0.6
0.2
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
1
2
3
4
4
5