k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 5

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
RAS, CAS,
~ WDQS3
~ RDQS3
BA0,BA1
A0 ~ A11
WDQS0
NC/RFU
Symbol
~ DQ31
RDQS0
CK, CK
~DM3
V
V
V
V
V
DM0
RFM
CKE
DQ0
RES
SEN
V
V
WE
MF
CS
ZQ
DDQ
SSQ
DDA
SSA
REF
DD
SS
Reference Resistor connection pin for On-die termination.
Output
Output
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Input/
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Mirror Function for clamshell mounting of DRAMs. VDDQ CMOS input.
Clock: CK and CK are differential clock inputs. CMD, ADD inputs are sampled on the crossing of the positive
edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both
directions of crossing). CK, CK should be maintained stable, except self-refresh mode
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device input buffers
and output drivers. Taking CKE Low provides Precharge Power-Down and Self Refresh operation (all banks
idle), or Active Power-Down (row Active in any bank). CKE is synchronous for power down entry and exit, and
for self refresh entry. CKE is asynchronous for self refresh exit. CKE must be maintained high throughout read
and write accesses. Input buffers, excluding CK, CK and CKE are disabled during power-down. Input buffers,
excluding CKE, are disabled during self refresh.
Chip Select: All commands are masked when CS is registered HIGH. CS provides for external bank selection
on systems with multiple banks. CS is considered part of the command code.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH
coincident with that input data during a Write access. DM is sampled on both edges of clock. Although DM
pins are input only, the DM loading matches the DQ and WDQS loading.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge command is
being applied.
Address Inputs: Provided the row address for Active commands and the column address and Auto Pre-
charge bit for Read/Write commands to select one location out of the memory array in the respective bank. A8
is sampled during a Precharge command to determine whether the Precharge applies to one bank (A8 LOW)
or all banks (A8 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1,BA2. The
address inputs also provide the op-code during Mode Register Set commands.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA7, CA9 . Column address CA8 is used for auto
precharge.
Data Input/ Output: Bi-directional data bus.
READ Data Strobe: Output with read data. RDQS is edge-aligned with read data.
WRITE Data Strobe: Input with write data. WDQS is center-aligned to the inout data.
No Connect: No internal electrical connection is present.
DQ Power Supply
DQ Ground
Power Supply
Ground
DLL Power Supply
DLL Ground
Reference voltage: 0.7*VDDQ ,
2 Pins : (H12) for Data input , (H1) for CMD and ADDRESS
Reset pin: RESET pin is a VDDQ CMOS input
Scan enable : Must tie to the ground in case not in use. VDDQ CMOS input.
Reserved for Mirror Function :
When the MF ball is tied low, RFM(H10) is recommended to be driven to logic low state.
When the MF ball is tied high, RAS(H3) switch to RFM and is recommended to be driven to logic low state
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Function
256M GDDR3 SDRAM
Rev. 1.3 May 2007