k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 21
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k4j55323qi
Manufacturer Part Number
k4j55323qi
Description
256mbit Gddr3 Sdram
Manufacturer
Samsung Semiconductor, Inc.
Datasheet
1.K4J55323QI.pdf
(54 pages)
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K4J55323QI
SCAN AC ELECTRICAL CHARACTERISTICS
*Note : 1. The parameter applies only when SEN is asserted.
Clock
Clock cycle time
Scan Command Time
Scan enable setup time
Scan enable hold time
Scan command setup time for SSH, SOE# and SOUT
Scan command hold time for SSH, SOE# and SOUT
Scan Capture Time
Scan capture setup Time
Scan capture hold Time
Scan Shift Time
Scan clock to valid scan output
Scan clock to scan output hold
2. Scan Enable should be issued earlier than other Scan Commands by 3ns.
(SSH in Scan Mode)
(Quad-load C/A)
Pins Under Test
(Dual-load C/A)
Note : To set the pre-defined ODT for C/A, a boundary scan mode should be issued after an appropriate ODT initialization sequence with RES and CKE signals
VDDQ
SOUT
VREF
SOE#
VDD
RES
CKE
CKE
SEN
SCK
PARAMETER/CONDITON
tATS
tATS
RESET at power - up
T = 200us
Figure 4. Scan Initialization Sequence
21 / 54
tSES
tSCS
tSCS
tSDS tSDH
tSDS tSDH
tSDS tSDH
Boundary Scan Mode
VALID
VALID
VALID
SYMBOL
tSEH
tSCH
tSCH
tSAC
tSOH
tSCK
tSES
tSCS
tSDS
tSCH
MIN
1.5
40
20
20
14
14
10
10
-
256M GDDR3 SDRAM
MAX
6
-
-
-
-
-
-
-
-
Rev. 1.3 May 2007
tSCS
tSCS
UNITS
tSCH
ns
ns
ns
ns
ns
ns
ns
ns
ns
Scan Out
Bit0
NOTES
1,2
1
1
1
1
1
1
1
1