k4j55323qi Samsung Semiconductor, Inc., k4j55323qi Datasheet - Page 48

• Manufacturer Part Number: k4j55323qi
• Description: 256mbit Gddr3 Sdram
• Manufacturer: Samsung Semiconductor, Inc.

K4J55323QI
Note :
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat-
ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure periods may affect reliability.
Recommended operating conditions (0°C ≤ Tc ≤ 85°C ; VDD/VDDQ=1.8V + 0.1V for -BC**, VDD/VDDQ=1.9V+ 0.1V
Note :
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VREF is expected to equal 70% of VDDQ for the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise on VREF
3. The DC values define where the input slew rate requirements are imposed, and the input signal must not violate these levels in order to maintain a valid
4. Input and output slew rate =3V/ns. If the input slew rate is less than 3V/ns, input timing may be compromised. All slew rate are measured between
5. VIH overshoot : VIH(max) = VDDQ + 0.5V for a pulse width
6. K4J55323QI-BC**
7. K4J55323QI-BJ**
8. V
11.0 AC & DC OPERATING CONDITIONS
11.1 ABSOLUTE MAXIMUM RATINGS
11.2 POWER & DC OPERATING CONDITIONS
Voltage on any pin relative to Vss
Voltage on V
Voltage on V
MAX Junction Temperature
Storage temperature
Power dissipation
Short Circuit Output Current
Device Supply voltage
Output Supply voltage
Device Supply voltage
Output Supply voltage
Reference voltage
DC Input logic high voltage
DC Input logic low voltage
Output logic low voltage
AC Input logic high voltage
AC Input logic low voltage
Input leakage current
Any input 0V-<V
(All other pins not under test = 0V)
Output leakage current
(DQs are disabled ; 0V-<V
may not exceed + 2 percent of the DC value. Thus, from 70% of VDDQ, VREF is allowed + 25mV for DC error and an additional +25mV for AC noise.
level. The inputs require the AC value to be achieved during signal transition edge and the driver should achieve the same slew rate through the AC
values.
Vih and Vil. DQ and DM input slew rate must not deviate from DQS by more than 10%. If the DQ,DM and DQS slew rate is less than 3V/ns, timing is
longer than referenced to the mid-point but to the VIL(AC) maximum and VIH(AC) minimum points.
VIL undershoot : VIL(min)=0.0V for a pulse width
OL(DC) max for -BJ** is 0.84V
DD
DDQ
Parameter
supply relative to Vss
IN
supply relative to Vss
Parameter
-< V
DDQ
OUT
-< V
DDQ
)
≤
500ps and the pulse width can not be greater than 1/3 of the cycle rate.
Symbol
V
V
V
V
V
V
V
V
OL(DC)
IH (DC)
V
V
IL (DC)
IH(AC)
IL(AC)
I
V
DDQ
DDQ
IOZ
REF
≤
DD
DD
I
Symbol
I
IN
500ps and the pulse width can not be greater than 1/3 of the cycle rate.
V
T
V
, V
I
P
DDQ
T
STG
OS
DD
D
J
OUT
48 / 54
0.69*V
V
V
REF
REF
Min
1.7
1.7
1.8
1.8
-5
-5
+0.15
-
-
+0.25
-
DDQ
-0.5 ~ V
Typ
1.8
1.8
1.9
1.9
-
-
-
-
-
-
-
-
-55 ~ +150
-0.5 ~ 2.5
-0.5 ~ 2.5
Value
+125
DDQ
50
4
256M GDDR3 SDRAM
+ 0.5V
0.71*V
V
V
REF
REF
Max
0.76
1.9
1.9
2.0
2.0
5
5
-
-
-0.15
-0.25
Rev. 1.3 May 2007
DDQ
Unit
uA
uA
V
V
V
V
V
V
V
V
V
V
for -BJ**
Unit
mA
°C
°C
W
V
V
V
)
Note
3,4,5
3,4,5
1,6
1,6
1,7
1,7
2
3
3
8