cx20493-35/app Conexant Systems, Inc., cx20493-35/app Datasheet - Page 87

• Manufacturer Part Number: cx20493-35/app
• Description: With Cx20493 Smartdaa?
• Manufacturer: Conexant Systems, Inc.

5.2.7
5.2.8
5.2.9
102247B
CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet
MSR - Modem Status Register (Addr = 6)
RBR - RX Buffer (Receiver Buffer Register) (Addr = 0, DLAB = 0)
THR - TX Buffer (Transmitter Holding Register) (Addr = 0, DLAB = 0)
The Modem Status Register (MSR) reports current state and change information of the
modem. Bits 4-7 supply current state and bits 0-3 supply change information. The change
bits are set to a 1 whenever a control input from the modem changes state from the last
MSR read by the host. Bits 0-3 are reset to 0 when the host reads the MSR or upon reset.
Whenever bits 0, 1, 2, or 3 are set to a 1, a Modem Status Interrupt (IIR0-IIR3 = 0) is
generated.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
The RX Buffer (RBR) is a read-only register at location 0 (with DLAB = 0). Bit 0 is the
least significant bit of the data, and is the first bit received.
The TX Buffer (THR) is a write-only register at address 0 when DLAB = 0. Bit 0 is the
least significant bit and the first bit sent.
This bit indicates the logic state of the DCD# (RLSD#) output. If Loopback is selected
This bit indicates the logic state of the RI# output. If Loopback is selected (MCR4 = 1),
This bit indicates the logic state of the DSR# output. If Loopback is selected (MCR4 =
This bit indicates the logic state of the CTS# output. If Loopback is selected (MCR4 =
This bit is set to a 1 when the DCD bit changes state since the MSR was last read by
This bit is set to a 1 when the RI bit changes from a 1 to a 0 state since the MSR was
This bit is set to a 1 when the DSR bit has changed since the MSR was last read by the
This bit is set to a 1 when the CTS bit has changed since the MSR was last read by the
(MCR4 = 1), this bit reflects the state of the Out2 bit in the MCR (MCR3).
this bit reflects the state of the Out1 bit in the MCR (MCR2).
1), this bit reflects the state of the DTR bit in the MCR (MCR0).
1), this bit reflects the state of the RTS bit in the MCR (MCR1).
the host.
last read by the host.
host.
host.
Data Carrier Detect (DCD).
Ring Indicator (RI).
Clear to Send (CTS).
Delta Data Carrier Detect (DDCD).
Trailing Edge of Ring Indicator (TERI).
Delta Clear to Send (DCTS).
Data Set Ready (DSR).
Delta Data Set Ready (DDSR).
Conexant
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