cx20493-35/app Conexant Systems, Inc., cx20493-35/app Datasheet - Page 81

• Manufacturer Part Number: cx20493-35/app
• Description: With Cx20493 Smartdaa?
• Manufacturer: Conexant Systems, Inc.

5.2
5.2.1
102247B
CX81801-7x/8x SmartV.XX Modem in 128-Pin LQFP with CX20493 in 32-Pin LQFP Data Sheet
Register Signal Definitions
IER - Interrupt Enable Register (Addr = 1, DLAB = 0)
The IER enables five types of interrupts that can separately assert the HINT output signal
(Table 5-2). A selected interrupt can be enabled by setting the corresponding enable bit to
a 1, or disabled by setting the corresponding enable bit to a 0. Disabling an interrupt in
the IER prohibits setting the corresponding indication in the IIR and assertion of HINT.
Disabling all interrupts (resetting IER0 - IER3 to a 0) inhibits setting of any Interrupt
Identifier Register (IIR) bits and inhibits assertion of the HINT output. All other system
functions operate normally, including the setting of the Line Status Register (LSR) and
the Modem Status Register (MSR).
Bits 7-4
Bit 3
Bit 2
Bit 1
Bit 0
Always 0.
This bit, when a 1, enables assertion of the HINT output whenever the Delta CTS
This bit, when a 1, enables assertion of the HINT output whenever the Overrun Error
This bit, when a 1, enables assertion of the HINT output when the Transmitter Empty
This bit, when a 1, enables assertion of the HINT output when the Receiver Data Ready
(MSR0), Delta DSR (MSR1), Delta TER (MSR2), or Delta DCD (MSR3) bit in the
Modem Status Register (MSR) is a 1. This bit, when a 0, disables assertion of HINT
due to setting of any of these four MSR bits.
(LSR1), Parity Error (LSR2), Framing Error (LSR3), or Break Interrupt (LSR4)
receiver status bit in the Line Status Register (LSR) changes state. This bit, when a 0,
disables assertion of HINT due to change of the receiver LSR bits 1-4.
bit in the Line Status Register (LSR5) is a 1. This bit, when a 0, disables assertion of
HINT due to LSR5.
bit in the Line Status Register (LSR0) is a1 or character timeout occurs in the FIFO
mode. This bit, when a 0, disables assertion of HINT due to the LSR0 or character
timeout.
Not used.
Enable Modem Status Interrupt (EDSSI).
Enable Receiver Line Status Interrupt (ELSI).
Enable Transmitter Holding Register Empty Interrupt (ETBEI).
Enable Receiver Data Available Interrupt (ERBFI) and Character
Timeout in FIFO Mode.
Conexant
5-3